Cirrus Logic AN150 - Manual (Page 7)

AN150
AN150REV2 7
(FRS) bit in the configuration register?
The FRS bit (bit 19 in the Configuration Register)
is used to select between two different sets of out-
put word rates. When running the ADC from a
4.9152 MHz clock, the FRS bit can be toggled with
a simple software switch to provide either 50 Hz or
60 Hz rejection in situations where this is applica-
ble. The default state of the FRS bit is zero. In this
mode, the word rates from the ADC are 7.5, 15, 30,
60, 120, 240, 480, 960, 1920, and 3840 samples/s
(when running from a 4.9152 MHz clock). When
the FRS bit is set to one, these word rates and their
corresponding filter characteristics scale by a factor
of 5/6, producing output word rates of 6.25, 12.5,
25, 50, 100, 200, 400, 800, 1600, and 3200 sam-
ples/s. All of the word rates and filter characteris-
tics in the part will also scale with the master clock
frequency. Setting the FRS bit in the configuration
register has the same effect as changing the clock
frequency by a factor of 5/6, without having to
change the hardware on the board.
How are the channel setup registers in the
converters used?
The channel setup registers each hold two 16-bit
“Setups”, which can be thought of as pre-defined
calibration and conversion instructions. These 16-
bit register spaces contain all of the information
needed by the converter to perform a conversion or
calibration in the desired operating mode. The bit
selections in the Setups allow the user to choose the
physical channel, gain range, polarity, and word
rate to convert with, as well as the desired state of
the two output latch pins. They also define whether
the current source used for detection of an open cir-
cuit should be turned on, and if a delay should be
added between the switching of the latch outputs
and the beginning of a conversion cycle. By de-
fault, all of these registers are initially set to convert
on channel 1 in the 1X, bipolar input range at an
output word rate of 120 samples/s with the latch
pins both set to ‘0’, the current source off, and no
delay time. These registers must be modified when
the part is to be operated in a mode other than the
default settings. An entire channel setup register
(two Setups) must be read or written all at once,
even if one of the Setups in the register is not being
modified. If a “write all” or “read all” command is
issued on the channel setup registers, all four of the
registers (eight Setups) must be written or read.
When issuing a conversion or calibration command
to the converter, the channel setup register pointer
(CSRP) bits indicate which Setup to follow when
performing the calibration or conversion. The con-
verter will configure itself according to the infor-
mation found in the indicated Setup, and perform
the desired operation. The Setups allow the user to
select from multiple converter settings without
having to re-configure the converter each time the
configuration (channel, gain setting, word rate,
etc.) needs to change.
How is the delay time (DT) bit in each Setup
used?
The delay time (DT) bit in each Setup register adds
a fixed amount of delay between the new state of
the output latch pins, and the start of a new conver-
sion cycle. This allows the user to control circuitry
on the front-end of the device with slower response
times or power-on times with the output latch bits
of the converter, and start the conversion after the
front-end circuitry has settled. The delay time is
fixed at 1280 master clock cycles (approximately
260
µ
s when running from a 4.9152 MHz clock)
when the FRS bit in the configuration register is set
to ‘0’. When the FRS bit is set to ‘1’, the delay time
is extended to 1536 clock cycles (approximately
312
µ
s when running from a 4.9152 MHz clock).
For circuitry that takes longer than this to power on
or switch, a “dummy” conversion at a different
word rate can be used to add some delay time, or
the latch bits can be controlled from the Configura-
tion Register.