An150 – Cirrus Logic AN150 User Manual

Page 5

AN150

AN150REV2

CS5531/32/33/34 datasheet lists the typical RMS
noise values for all combinations of gain range and
word rate.

In the 32X and 64X gain ranges, the amplifier noise
dominates, and the modulator noise is not very sig-
nificant. As the gain setting decreases, the amplifi-
er noise becomes less significant, and the
modulator becomes the dominant noise source in
the 1X and 2X gain ranges. The noise density from
the amplifier and the modulator for word rates of
120 samples/s and lower can be calculated using
Equation 3.

In Equation 3, G refers to the gain setting of the
PGIA. N

refers to the amplifier noise, and N

re-

fers to the modulator noise. By using the noise
numbers at the beginning of this section, a noise
density number can be found for any gain range
setting. The typical RMS noise for a given word
rate can be estimated by multiplying the noise den-
sity at the desired gain range by the square root of
the filter’s corner frequency for that word rate. This
estimate does not include the noise that is outside
the filter bandwidth, but it can give a rough idea of
what the typical noise would be for those settings.
The true RMS noise number will be slightly higher,
as indicated by the RMS noise tables in the
datasheet.

The apparent noise numbers seen at the output of
the converter will be affected by the setting of the
internal gain register of the part. The typical RMS
noise numbers calculated in this section and shown
in the datasheet’s RMS noise tables correspond to
the noise seen at the converter’s output using a gain
register setting of approximately 1.0.

What factors affect the input current on the

analog inputs?

In the 1X gain range, the inputs are buffered with a
rough-fine charge scheme. With this input struc-
ture, the modulator sampling capacitor is charged
in two phases. During the first (rough) phase, the
capacitor is charged to approximately the correct
value using the 1X buffer amplifier, and the neces-
sary current is provided by the buffer output to the
sampling capacitor. During the second (fine) phase,
the capacitor is connected directly to the input, and
the necessary current to charge the capacitor to the
final value comes from the AIN+ and AIN- lines.
The size of the sampling capacitor, the offset volt-
age of the buffer amplifier, and the frequency at
which the front-end switches are operating can be
multiplied together (CxVxF) to calculate the input
current. The buffer amplifier’s offset voltage and
the modulator sampling capacitor size are a func-
tion of the silicon manufacturing process, and can-
not be changed. The frequency at which the
switches are operating is determined directly by the
master clock for the part, and is the only variable
that users can modify which will have an effect on
the input current in this mode. The input current
specified in the datasheet assumes a 4.9152 MHz
master clock.

In the 2X-64X gain ranges, the input current is due
to small differences in the silicon that makes up the
chopping switches on the front end of the amplifier.
The difference between these switches produces a
small charge injection current on the analog inputs.
The frequency at which the switches are operating
is derived directly from the master clock of the part,
and the input current will change as the master
clock frequency changes. Higher master clock fre-
quencies will produce higher input currents. Like-
wise, changes in the VA+ and VA- supply voltages
will change the amount of charge injection that is
produced by the switches, and higher supply volt-
ages will produce more current on the inputs. The
input current specified in the datasheet assumes a
4.9152 MHz master clock and 5 V between the

Noise Density

(

)

(

)

----------------------------------------------------

Equation 3. Noise Density