Cirrus Logic AN150 - Manual (Page 6)

AN150
6 AN150REV2
VA+ and VA- supply pins.
What factors affect the input current on the
voltage reference inputs?
The input structure on the VREF pins is similar to
the input structure for the 1X gain range. The inputs
are buffered with a rough-fine charge scheme.
However, the size of the capacitor (C) in the equa-
tion CxVxF changes with the setting of the VRS bit
in the configuration register. With the VRS bit set
to ‘1’, the capacitor size is cut in half, which also
reduces the VREF input current by 1/2. Like the an-
alog input current, the VREF input current will
change with clock frequency, and is specified with
a 4.9152 MHz clock.
How do the offset and gain register settings
affect the input range of the converter?
The offset and gain registers have a direct effect on
the output codes of the converter. Because of their
effects on the output codes from the converter, they
also have an apparent effect on the input voltage
span of the converter.
The contents of the offset registers are 24-bit 2’s
complement numbers (with a trailing byte of 0’s to
extend the register length to 32 bits) that shift the
output codes from the converter up or down by a
certain amount. The value in the offset register for
a given channel times a scaling value of
1.83007966 will be subtracted from every conver-
sion on that channel before it is output from the
converter. Because this shifts the output of the con-
verter, it will also shift the input span up or down,
depending on the contents of the offset register.
The corresponding effect on the input voltage de-
pends on both the input span of the converter, and
the gain register setting. The multiplication factor
of 1.83007966 is compensation for the effects of
the digital filter on this register. The offset register
may be used to remove a large bridge offset, or oth-
er offset errors in a system.
Example: With an offset register setting of
0x00000000, the measured output code from the
converter with a given input voltage is 0x000100
(256 decimal). When the offset register is set to
0x00001E00 (30 decimal, after truncating the last
byte), the expected shift in output code from the
converter would be 1.83007966 * 0x00001E =
0x000036 (54 decimal). Subtracting this from the
original output code gives 0x000100 - 0x000036 =
0x0000CA (202 decimal).
The contents of the gain registers are 30-bit fixed-
point numbers which can range from 0 to 64 - 2
-24
when expressed as decimal numbers (with two
leading 0’s to extend the register length to 32 bits).
Although the maximum gain register setting is
nearly 64, gain register settings above 40 should
not be used. The gain register has a scaling effect
on the output codes of the converter. After subtract-
ing the contents of the offset register, every conver-
sion is multiplied by the gain register for that
particular channel. This changes the slope of the
converter, and has an inverse proportional relation-
ship to the input span of the converter, as seen in
Equation 1, where the decimal equivalent of the
gain register is represented with the variable R
G
.
Example: With a gain register setting of
0x01000000 (1.0 decimal) and a given input volt-
age, the output code from the converter is
0x009C40 (40,000 decimal). If the gain register is
changed to 0x01C00000 (1.75 decimal), the output
code from the converter becomes 0x009C40 * 1.75
= 0x011170 (70,000 decimal). Thus, the effective
input range has also been scaled by 1/1.75.
Because this multiplication is done after the sub-
traction of the offset register, the gain register set-
ting has a direct effect on the offset introduced by
the offset register as well. It is for this reason that
any adjustments to the offset register should take
into account the gain register value, as well as the
1.83007966X filter gain factor that will be applied
afterwards.
What is the purpose of the Filter Rate Select