Cirrus Logic CS5331A - Manual (Page 15)

DS138F6 15
CS5330A/31A
5. REFERENCES
1. Area Efficient Decimation Filter for an 18-Bit Delta- Sigma ADC, by K. Lin and J. J. Paulos. Paper presented
at the 98th Convention of the Audio Engineering Society, February 1995.
2. An 18-Bit, 8-Pin Stereo Digital-to-Analog Converter, by J. J. Paulos, A. W. Krone, G. D. Kamath and S. T.
Dupuie. Paper presented at the 97th Convention of the Audio Engineering Society, November 1994.
3. An 18-Bit Dual-Channel Oversampling Delta-Sigma A/D Converter, with 19-Bit Mono Application Example,
by Clif Sanchez. Paper presented at the 87th Convention of the Audio Engineering Society, October 1989.
4. The Effects of Sampling Clock Jitter on Nyquist Sampling Analog-to-Digital Converters, and on Oversam-
pling Delta Sigma ADC’s, by Steven Harris. Paper presented at the 87th Convention of the Audio Engineer-
ing Society, October 1989.
5. A Stereo 16-bit Delta-Sigma A/D Converter for Digital Audio, by D. R. Welland, B. P. Del Signore, E. J.
Swanson, T. Tanaka, K. Hamashita, S. Hara, K. Takasuka. Paper presented at the 85th Convention of the
Audio Engineering Society, November 1988.
6. PACKAGE DESCRIPTIONS
Millimeters Inches
DIM MIN MAX MIN MAX
A 5.15 5.35 0.203 0.210
B 1.27 TYP 0.050 TYP
C 0 0.25 0 0.010
D 1.77 1.88 0.070 0.074
E 0.33 0.51 0.013 0.020
F .15 0.25 0.006 0.010
G 0° 8° 0° 8°
H 5.18 5.4 0.204 0.213
I 0.48 0.76 0.019 0.030
J 7.67 8.1 0.302 0.319
Note: The EIAJ Package is not a standard JEDEC package size.
8-Pin
SOIC
F
G
J
I
H
B
A
E
D
C