Cirrus Logic CS48AU2B - Manual (Page 19)

CS48AU2B Data Sheet
Dedicated 32-bit Audio DSP for Audyssey Laboratories Technology
DS876F3 Copyright 2009 Cirrus Logic 19
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5.15 Switching Characteristics — Digital Audio Output Port
Parameter Symbol Min Max Unit
DAO_MCLK period T
daomclk
40 - ns
DAO_MCLK duty cycle - 45 55 %
DAO_SCLK period for Master or Slave mode
1
1. Master mode timing specifications are characterized, not production tested.
T
daosclk
40 - ns
DAO_SCLK duty cycle for Master or Slave mode
1
- 40 60 %
Master Mode (Output A1 Mode)
1,2
2. Master mode is defined as the CS48DVxx driving both DAO_SCLK, DAO_LRCLK. When MCLK is an input, it is divided to produce
DAO_SCLK, DAO_LRCLK.
DAO_SCLK delay from DAO_MCLK rising edge,
DAO_MCLK as an input t
daomsck
- 19 ns
DAO_LRCLK delay from DAO_SCLK transition, respectively 3
3. This timing parameter is defined from the non-active edge of DAO_SCLK. The active edge of DAO_SCLK is the point at which the
data is valid.
t
daomstlr
- 8 ns
DAO_SCLK delay from DAO_LRCLK transition, respectively
3
t
daomlrts
- 8 ns
DAO1_DATA[3..0], DAO2_DATA[1..0]
delay from DAO_SCLK transition
3
t
daomdv
- 10 ns
Slave Mode (Output A0 Mode)
4
4. Slave mode is defined as DAO_SCLK, DAO_LRCLK driven by an external source.
DAO1_DATA[3..0], DAO2_DATA[1..0]
delay from DAO_SCLK transition
3
t
daosdv
- 15 ns
DAO_LRCLK delay from DAO_SCLK transition, respectively
3
t
daosstlr
- 30 ns
DAO_SCLK delay from DAO_LRCLK transition, respectively
3
t
daoslrts
- 15 ns
DAO_MCLK
DAO_SCLK
DAO_LRCLK
DAOn_DATAn
t
daomlclk
t
daomsck
t
daomdv
t
daomlrts
DAO_MCLK
DAO_SCLK
DAO_LRCLK
DAOn_DATAn
t
daomclk
t
daomsck
t
daomstlr
Note: In these diagrams, Falling edge is the inactive edge of DAO_SCLK