Cirrus Logic CS48AU2B - Manual (Page 13)

CS48AU2B Data Sheet
Dedicated 32-bit Audio DSP for Audyssey Laboratories Technology
DS876F3 Copyright 2009 Cirrus Logic 13
CONFIDENTIAL
CONFIDENTI
A
L
DRA
FT
DELP
HI
5.8 Switching Characteristics — Internal Clock
Parameter Symbol Min Max Unit
Internal DCLK frequency
1
CS48AU2B-CQZ
1. After initial power-on reset, F
dclk
= F
xtal
. After initial kickstart commands, the PLL is locked to max F
dclk
and remains locked until
the next power-on reset.
F
dclk
-
F
xtal
150
MHz
Internal DCLK period
1
CS48AU2B-CQZ
DCLKP -
6.7 1/F
xtal
ns