Cirrus Logic CS485xx - Manual (Page 8)

8 DS734F5
4.3 DSP I/O Description
4.2.2 Digital Audio Output Port (DAO)
Each version of the CS485xx supports a different number of output channels. Refer to Table 3-1 for more details.
DAO port supports PCM resolutions of up to 32-bits. The port supports sample rates (Fs) as high as 192 kHz. The port
can be configured as an independent clock domain mastered by the DSP, or as a clock slave if an external MCLK or SCLK/
LRCLK source is available. One of the serial audio pins can be re-configured as a S/PDIF transmitter that drives a biphase
encoded S/PDIF signal (data with embedded clock on a single line).
The DAO also supports a time division multiplexed (TDM) one-line data mode, that packs multiple channels of PCM audio
on a single data line.
4.2.3 Serial Control Port (I 2 C ™ or SPI ™ )
The on-chip serial control port is capable of operating as master or slave in either SPI ™ or I 2 C ™ modes. Master/
Slave operation is chosen by mode select pins when the CS485xx comes out of Reset. The serial clock pin can
support frequencies as high as 25 MHz in SPI mode (SPI clock speed must always be
≤ (F
dclk
/2)). The CS485xx
serial control port also includes a pin for flow control of the communications interface (SCP_BSY) and a pin to
indicate when the DSP has a message for the host (SCP_IRQ).
4.2.4 GPIO
Many of the CS485xx peripheral pins are multiplexed with GPIO. Each GPIO can be configured as an output, an input, or
an input with interrupt. Each input-pin interrupt can be configured as rising edge, falling edge, active-low, or active-high.
4.2.5 PLL-based Clock Generator
The low-jitter PLL generates integer or fractional multiples of a reference frequency which are used to clock the DSP core
and peripherals. Through a second PLL divider chain, a dependent clock domain can be output on the DAO port for driving
audio converters. The CS485xx defaults to running from the external reference frequency and is switched to use the PLL
output after overlays have been loaded and configured, either through master boot from an external FLASH or through
host control. A built-in crystal oscillator circuit with a buffered output is provided. The buffered output frequency ratio is
selectable between 1:1 (default) or 2:1.
4.2.6 Hardware Watchdog Timer
The CS485xx has an integrated watchdog timer that acts as a “health” monitor for the DSP. The watchdog timer must be
reset by the DSP before the counter expires, or the entire chip is reset. This peripheral ensures that the CS485xx will reset
itself in the event of a temporary system failure. In stand-alone mode (that is, no host MCU), the DSP will reboot from
external FLASH. In slave mode (that is, host MCU present) a GPIO will be used to signal the host that the watchdog has
expired and the DSP should be rebooted and re-configured.
4.3 DSP I/O Description
4.3.1 Multiplexed Pins
Many of the CS485xx family pins are multi-functional. For details on pin functionality, refer to the CS485xx Hardware
User’s Manual.
4.3.2 Termination Requirements
Open-drain pins on the CS485xx must be pulled high for proper operation. Refer to the CS485xx Hardware User’s Manual
to identify which pins are open-drain and what value of pull-up resistor is required for proper operation.
Mode select pins in the CS485xx family are used to select the boot mode upon the rising edge from reset. A detailed
explanation of termination requirements for each communication mode select pin can be found in the CS485xx Hardware
User’s Manual.