Cirrus Logic CS485xx - Manual (Page 12)

12 DS734F5
5.9 Switching Characteristics—Serial Control Port–SPI Slave Mode
5.9 Switching Characteristics—Serial Control Port–SPI Slave Mode
Figure 5-3. Serial Control Port–SPI Slave Mode Timing
Internal DCLK period 1 DCLKP — — ns
CS4852x-CQZ
CS4854x-CQZ
CS4856x-CQZ
CS4854x-DQZ
CS4856x-DQZ 6.7
6.7
6.7
6.7
6.7 1/F
xtal
1/F
xtal
1/F
xtal
1/F
xtal
1/F
xtal
1.After initial power-on reset, F
dclk
= F
xtal
. After initial kick-start commands, the PLL is locked to max F
dclk
and remains locked until the next power-on
reset.
Parameter Symbol Min Typical Max Units
SCP_CLK frequency 1
1.The specification f
spisck
indicates the maximum speed of the hardware. The system designer should be aware that the actual maximum speed of the
communication port may be limited by the firmware application. Flow control using the SCP_BSY# pin should be implemented to prevent overflow of
the input data buffer. At boot the maximum speed is F
xtal
/3.
f
spisck
— — 25 MHz
SCP_CS# falling to SCP_CLK rising t
spicss
24 — — ns
SCP_CLK low time t
spickl
20 — — ns
SCP_CLK high time t
spickh
20 — — ns
Setup time SCP_MOSI input t
spidsu
5 — — ns
Hold time SCP_MOSI input t
spidh
5 — — ns
SCP_CLK low to SCP_MISO output valid t
spidov
— — 11 ns
SCP_CLK falling to SCP_IRQ# rising t
spiirqh
— — 20 ns
SCP_CS# rising to SCP_IRQ# falling t
spiirql
0 — — ns
SCP_CLK low to SCP_CS# rising t
spicsh
24 — — ns
SCP_CS# rising to SCP_MISO output high-Z t
spicsdz
— 20 — ns
SCP_CLK rising to SCP_BSY# falling t
spicbsyl
— 3*DCLKP+20 — ns
Parameter Symbol Min Max Unit
SCP_BSY#
SCP_CS#
SCP_CLK
SCP_MOSI
SCP_MISO
SCP_IRQ#
0 1 2 6 7 0 5 6 7
t
spicss
t
spickl
t
spickh
t
spidsu
t
spidh t
spidov
A6 A5 A0 R/W MSB LSB
MSB LSB
t
spicsh
t
spibsyl
t
spiirql
t
spiirqh
f
spisck
t
spicsdz