Cirrus Logic CS485xx - Manual (Page 7)

7 DS734F5
4 Hardware Functional Description
4 Hardware Functional Description
4.1 DSP Core
The CS485xx family DSPs are single-core DSP with separate X and Y data and P code memory spaces. The DSP core
is a high-performance, 32-bit, user-programmable, fixed-point DSP that is capable of performing two
multiply-and-accumulate (MAC) operations per clock cycle. The DSP core has eight 72-bit accumulators, four X- and four
Y-data registers, and 12 index registers.
The DSP core is coupled to a flexible DMA engine. The DMA engine can move data between peripherals such as the serial
control port (SCP), digital audio input (DAI) and digital audio output (DAO), or any DSP core memory, all without the
intervention of the DSP. The DMA engine off loads data move instructions from the DSP core, leaving more MIPS available
for signal processing instructions.
CS485xx family functionality is controlled by application codes that are stored in on-board ROM or downloaded to the
CS485xx from a host controller or external serial FLASH/EEPROM.
Users can develop their applications using DSP Composer to create the processing chain and then compile the image into
a series of commands that are sent to the CS485xx through the SCP. The processing application can either load modules
(matrix-processors, virtualizers, post-processors) from the DSPs on-board ROM, or custom firmware can be downloaded
through the SCP.
The CS485xx is suitable for a variety of audio post-processing applications such as automotive head-ends, automotive
amplifiers, and boom boxes.
4.1.1 DSP Memory
The DSP core has its own on-chip data and program RAM and ROM and does not require external memory for
post-processing applications.
The Y-RAM and P-RAM share a single block of memory that can be configured to make Y and P equal in size, or more
memory can be allocated for Y-RAM in 2kword blocks.
4.1.2 DMA Controller
The powerful 8-channel DMA controller can move data between 8 on-chip resources. Each resource has its own arbiter:
X, Y, and P RAMs/ROMs and the peripheral bus. Modulo and linear addressing modes are supported, with flexible start
address and increment controls. The service intervals for each DMA channel, as well as up to 6 interrupt events, are
programmable.
4.2 On-chip DSP Peripherals
4.2.1 Digital Audio Input Port (DAI)
Each version of the CS485xx supports a different number of input channels. Refer to Table 3-1 for more details.
The DAI port supports a wide variety of data input formats at sample rates (Fs) as high as 192 kHz. The port is capable of
accepting PCM or DSD formats. Up to 32-bit word lengths are supported. DSD is supported and internally converted to
PCM before processing. The DAI also supports a time division multiplexed (TDM) one-line data mode, that packs PCM
audio on a single data line (the total number possible depends on the ratio of SCLK to LRCLK and the version of chip. For
example on the CS48520 only 4 ch of PCM are supported in one line mode and on the CS48560 up to 8 channels are
supported.).
The port has two independent slave-only clock domains. Each data input can be independently assigned to a clock
domain. The sample rate of the input clock domains can be determined automatically by the DSP, off-loading the task of
monitoring the SPDIF receiver from the host. A time-stamping feature allows the input data to be sample-rate converted
via software.