Cirrus Logic CS44800 - Manual (Page 71)

DS632F1 71
CS44800
The Channel Delay bits allow delay adjustment of each of the PWMOUT differential signal pairs, PW-
MOUTAx+/PWMOUTAx- from the associated PWMOUTBx+/PWMOUTBx-. The value of this register de-
termines the amount of delay inserted in the output path. The effective delay is calculated by multiplying
the register value by the period of the PWM_MCLK. This parameter can only be changed when all mod-
ulators and associated logic are in the power-down state by setting the PDN bit in the register
“Clock Con-
figuration and Power Control (address 02h)” on page 51 to a 1b. Attempts to write this register while the
PDN is not set will be ignored.
Binary Code Delay Setting(multiply by PWM_MCLK period)
00000 0 - no delay
00110 6
11000 24
11111 31
Table 16. Channel Delay Settings