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4 de-emphasis control (dem[1:0]), 6 ramp configuration (address 05h), 1 ramp-up/down setting (ramp[1:0]) – Cirrus Logic CS44800 User Manual

Page 54: 2 ramp speed (ramp_spd[1:0])

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54

DS632F1

CS44800

7.5.4

De-Emphasis Control (DEM[1:0])

Default = 00
00 - no de-emphasis
01 - 32 kHz de-emphasis filter
10 - 44.1 kHz de-emphasis filter
11 - 48 kHz de-emphasis filter
Function:

Enables the appropriate digital filter to maintain the standard 15 ms/50 ms digital de-emphasis filter re-
sponse.

7.6

Ramp Configuration (address 05h)

7.6.1

Ramp-Up/Down Setting (RAMP[1:0])

Default = 00
00 - Ramp-up and ramp-down are disabled
01 - Ramp-up is disabled. Ramp-down is enabled.
10 - Reserved
11 - Ramp-up and ramp-down are enabled. Note that after a ramp-up sequence has completed, audio will
not play until RAMP[1:0] is set to 01.

Function:

When ramping is enabled, the duty cycle of the output PWM signal is increased (ramp-up) or decreased
(ramp-down) at a rate determined by the Ramp Speed variable (RAMP_SPDx). This function is used in
single-ended applications to reduce pops in the output caused by the DC-blocking capacitor. When the
ramp-up/down function is disabled in single-ended applications, there will be an abrupt change in the out-
put signal. Refer to Section 5.1.1

.

If ramp-up or down is not needed, as in a full-bridge application, these bits should be set to 00. If ramp-
up or down is needed, as in a single-ended half-bridge application, these bits must be used in the proper
sequence as outlined in

“Recommended Power-Up Sequence” on page 43

and

“Recommended Power-

Down Sequence” on page 45

.

7.6.2

Ramp Speed (RAMP_SPD[1:0])

Default = 01
00 - Ramp speed = approximately 0.1 seconds
01 - Ramp speed = approximately 0.2 seconds
10 - Ramp speed = approximately 0.3 seconds
11 - Ramp speed = approximately 0.65 seconds

Function:

This feature is used in single-ended applications to reduce pops in the output caused by the DC-blocking
capacitor. The Ramp Speed sets the time for the PWM signal to linearly ramp-up and down from the bias
point (50% PWM duty cycle). Refer to Section 5.1.1

7

6

5

4

3

2

1

0

RESERVED

RESERVED

RESERVED

RAMP1

RAMP0

RESERVED

RAMP_SPD1

RAMP_SPD0