Cirrus Logic CS44800 - Manual (Page 7)

DS632F1 7
CS44800
LIST OF TABLES
Table 1. Common DAI_MCLK Frequencies .............................................................................................. 25
Table 2. DAI Serial Audio Port Channel Allocations ................................................................................. 27
Table 3. Load Compensation Example Settings ....................................................................................... 32
Table 4. Typical PWM Switch Rate Settings ............................................................................................. 34
Table 5. Digital Audio Interface Formats ................................................................................................... 53
Table 6. Master Integer Volume Settings .................................................................................................. 57
Table 7. Master Fractional Volume Settings ............................................................................................. 58
Table 8. Channel Integer Volume Settings ............................................................................................... 59
Table 9. Channel Fractional Volume Settings ........................................................................................... 60
Table 10. Limiter Attack Rate Settings ...................................................................................................... 62
Table 11. Limiter Release Rate Settings ................................................................................................... 62
Table 12. Channel Load Compensation Filter Coarse Adjust ................................................................... 63
Table 13. Channel Load Compensation Filter Fine Adjust ........................................................................ 63
Table 14. PWM Minimum Pulse Width Settings ........................................................................................ 70
Table 15. Differential Signal Delay Settings .............................................................................................. 70
Table 16. Channel Delay Settings ............................................................................................................. 71
Table 17. Power Supply Sync Clock Divider Settings ............................................................................... 74
Table 18. Decimator Shift/Scale Coefficient Calculation Examples .......................................................... 75