Cirrus Logic CS44800 - Manual (Page 29)

DS632F1 29
CS44800
4.4.1.3 Right-Justified Data Format
In the right-justified format, data is received most significant bit first and with the least significant bit pre-
sented on the last DAI_SCLK before the DAI_LRCK transition and is valid on the rising edge of
DAI_SCLK. For the right-justified format, the left channel data is presented when DAI_LRCK is high and
the right channel data is presented when DAI_LRCK is low. Either 16 bits per sample or 24 bits per sam-
ple are supported.
4.4.1.4 One Line Mode #1
In One Line mode #1 format, data is received most significant bit first on the first DAI_SCLK after a
DAI_LRCK transition and is valid on the rising edge of DAI_SCLK. DAI_SCLK must operate at a 128Fs
rate. DAI_LRCK identifies the start of a new frame and is equal to the sample period. DAI_LRCK is sam-
pled as valid on the same clock edge as the most significant bit of the first data sample and must be held
high for 64 DAI_SCLK periods. Each time slot is 20 bits wide, with the valid data sample left-justified within
the time slot. Valid data lengths are 16, 18, or 20 bits. Valid samples rates for this mode are 32 kHz to
96 kHz.
Left Channel
Right Channel
6 5 4 3 2 1 0 9 8 7 15 1 4 13 12 11 10 6 5 4 3 2 1 0 9 8 7 15 14 13 12 11 10 DAI_SDINx
DAI_LRCK
DAI_SCLK
Figure 19. Right-Justified Serial Audio Formats
Right-Justified Mode, Data Valid on Rising Edge of DAI_SCLK
Bits/Sample SCLK Rate(s)
16 32, 48, 64, 128, 256 Fs
24 48, 64, 128, 256 Fs
PWMOUTB3
DAI_LRCK
DAI_SCLK
LSB MSB
20 clks
64 clks 64 clks
LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB MSB
20 clks 20 clks 20 clks 20 clks 20 clks
DAI_SDIN4
DAI_SDIN1
PWMOUTA1 PWMOUTB1 PWMOUTA2 PWMOUTB2 PWMOUTA3
LSB MSB
20 clks
LSB MSB
20 clks
PWMOUTA4 PWMOUTB4
MSB
Left Channels Right Channels
Figure 20. One Line Mode #1 Serial Audio Format