6 mclk divide by 2, 5 interface control 1 (address 06h), 1 master/slave mode – Cirrus Logic CS43L22 User Manual
Page 40: 2 sclk polarity, 3 dsp mode, 4 dac interface format, P 40
40
DS792F2
CS43L22
Confidential Draft
3/4/10
7.4.6
MCLK Divide By 2
Divides the input MCLK by 2 prior to all internal circuitry.
Note:
In Slave Mode, this bit is ignored when the AUTO bit (
) is disabled.
7.5
Interface Control 1 (Address 06h)
7.5.1
Master/Slave Mode
Configures the serial port I/O clocking.
7.5.2
SCLK Polarity
Configures the polarity of the SCLK signal.
7.5.3
DSP Mode
Configures a data-packed interface format for the DAC.
Notes:
1.
Select the audio word length using the AWL[1:0] bits (
“Audio Word Length” on page 41
2.
The interface format for the DAC must be set to “Left-Justified” when DSP Mode is enabled.
7.5.4
DAC Interface Format
Configures the digital interface format for data on SDIN.
Note:
Select the audio word length for Right Justified using the AWL[1:0] bits (
).
MCLKDIV2
MCLK signal into DAC
0
No divide
1
Divided by 2
Application:
“Serial Port Clocking” on page 29
7
6
5
4
3
2
1
0
M/S
INV_SCLK
Reserved
DSP
DACDIF1
DACDIF0
AWL1
AWL0
M/S
Serial Port Clocks
0
Slave (input ONLY)
1
Master (output ONLY)
INV_SCLK
SCLK Polarity
0
Not Inverted
1
Inverted
DSP
DSP Mode
0
Disabled
1
Enabled
Application:
DACDIF[1:0]
DAC Interface Format
00
Left Justified, up to 24-bit data
01
I²S, up to 24-bit data
10
Right Justified
11
Reserved
Application: