10 i, Cs4391a – Cirrus Logic CS4391A User Manual
Page 29
CS4391A
DS600PP3
29
Note:These clocking ratios are only available inControl Port Mode when the MCLK Divide bit is enabled.
Sample Rate
(kHz)
MCLK (MHz)
See Note
256x
384x
512x
768x
1024x
32
8.1920
12.2880
16.3840
24.5760
32.7680
44.1
11.2896
16.9344
22.5792
33.8688
45.1584
48
12.2880
18.4320
24.5760
36.8640
49.1520
Table 8. Single Speed (4 to 50 kHz sample rates) Common Clock Frequencies
Sample Rate
(kHz)
MCLK (MHz)
See Note
128x
192x
256x
384x
512x
64
8.1920
12.2880
16.3840
24.5760
32.7680
88.2
11.2896
16.9344
22.5792
33.8688
45.1584
96
12.2880
18.4320
24.5760
36.8640
49.1520
Table 9. Double Speed (50 to 100 kHz sample rates) Common Clock Frequencies
Sample Rate
(kHz)
MCLK (MHz)
See Note
64x
96x
128x
192x
256x
176.4
11.2896
16.9344
22.5792
33.8688
45.1584
192
12.2880
18.4320
24.5760
36.8640
49.1520
Table 10. Quad Speed (100 to 200 kHz sample rates) Common Clock Frequencies
M3
M1
(DIF1)
M0
(DIF0)
DESCRIPTION
FORMAT
FIGURE
0
0
0
Left Justified, up to 24-bit data
0
0
0
1
I
2
S, up to 24-bit data
1
0
1
0
Right Justified, 16-bit Data
2
0
1
1
Right Justified, 24-bit Data
3
Table 11. Single Speed (4 to 50 kHz) Digital Interface Format, Stand-Alone Mode Options
M3
M2
(DEM)
DESCRIPTION
FIGURE
0
0
No De-Emphasis
0
1
De-Emphasis Enabled
Table 12. Single Speed Only (4 to 50 kHz) De-Emphasis, Stand-Alone Mode Options
M3
M2
M1
M0
DESCRIPTION
FORMAT
FIGURE
1
0
0
0
Left Justified up to 24-bit data
0
1
0
0
1
I
2
S up to 24-bit data
1
1
0
1
0
Right Justified 16-bit data
2
1
0
1
1
Right Justified 24-bit data
3
Table 13. Double Speed (50 to 100 kHz) Digital Interface Format, Stand-Alone Mode Options