Cirrus Logic CS4348 - Manual (Page 14)

14
CS4344/5/8
Figure 9. CS4348 Data Format (Right Justified 16)
LRCK
SCLK
Left Channel
Right Channel
SDATA 6 5 4 3 2 1 0 9 8 7 15 14 13 12 11 10 6 5 4 3 2 1 0 9 8 7 15 14 13 12 11 10
32 clocks
Internal SCLK Mode External SCLK Mode
Right Justified, 16-Bit Data
INT SCLK = 32 Fs if
MCLK/LRCK = 1024, 512, 256, 128, or 64
INT SCLK = 48 Fs if
MCLK/LRCK = 768, 384, 192, or 96
INT SCLK = 72 Fs if
MCLK/LRCK = 1152 Right Justified, 16-Bit Data
Data Valid on Rising Edge of SCLK
SCLK Must Have at Least 32 Cycles per LRCK Period