Cirrus Logic CS4348 - Manual (Page 10)

10
CS4344/5/8
Figure 3. External Serial Mode Input Timing
Figure 4. Internal Serial Mode Input Timing
Figure 5. Internal Serial Clock Generation
sclkh
t
slrs
t
slrd
t
sdlrs
t sdh
t
sclkl
t
SDATA
SCLK
LRCK
SDATA
*INTERNAL SCLK
LRCK
sclkw
t
sdlrs
t
sdh
t
sclkr
t
The SCLK pulses shown are internal to the CS4344/5/8.
SDATA
LRCK
MCLK
*INTERNAL SCLK
1
N
2
N
* The SCLK pulses shown are internal to the CS4344/5/8.
N equals MCLK divided by SCLK