Cirrus Logic CDB42L55 - Manual (Page 9)

DS773DB1 9
CDB42L55
3.2 Analog In to S/PDIF or PSIA Out
The CS42L55 analog front-end performance can be tested by selecting the “SPDIF In to Analog Out --
Analog In to S/PDIF Out” or “PSIA In to Analog Out -- Analog In to PSIA Out” quick setup file provided
with the software package. Note: The Control Port Compensation script for the associated VA supply
must also be selected. The script configures the digital clock and data signal routing on the board as shown
in
Figure 3 . The quick setup scripts provided in the software assume that a 24.000 MHz on-board oscillator
is populated in Y1.
A S/PDIF input must be provided as the S/PDIF Tx (CS8406) uses the RMCK signal from the S/PDIF Rx
(CS8416) for synchronization in this configuration.
Figure 3. Analog In to S/PDIF or PSIA Out
CS42L55
SCLK
LRCK
Rx SRC
(CS8421)
PSIA Rx (J40)
RX.SCLK
RX.LRCK
RX.SDIN
24 MHz
(on-board osc.)
12 MHz MCLK
ADC.SDOUT
S/PDIF Tx
(CS8406)
TX.SCLK
TX.LRCK
TX.SDIN
S/PDIF
OUT
AIN1B
AIN1A
AIN2A
AIN2B
AIN1A
AIN1B
AIN2A
AIN2B
FPGA PLL &
Divider
(Master)
(Slave)
(Slave)