Cirrus Logic CDB42L55 - Manual (Page 2)

2 DS773DB1
CDB42L55
TABLE OF CONTENTS
1. QUICK START GUIDE ........................................................................................................................... 4
2. SYSTEM OVERVIEW ............................................................................................................................. 5
2.1 Control Port and Board Configuration .............................................................................................. 5
2.2 Power ............................................................................................................................................... 5
2.3 Digital Input ....................................................................................................................................... 5
2.3.1 CS8416 S/PDIF Digital Audio Receiver .................................................................................. 5
2.3.2 CS8421 Sample Rate Converter (Tx SRC to CS42L55) ......................................................... 6
2.4 Digital Output .................................................................................................................................... 6
2.4.1 CS8406 S/PDIF Digital Audio Transmitter .............................................................................. 6
2.4.2 CS8421 Sample Rate Converter (Rx SRC from CS42L55) .................................................... 6
2.5 FPGA ................................................................................................................................................ 6
2.6 Oscillator ........................................................................................................................................... 7
2.7 CS42L55 Audio CODEC .................................................................................................................. 7
3. CONFIGURATION OPTIONS ................................................................................................................. 8
3.1 S/PDIF or PSIA In to Analog Out ...................................................................................................... 8
3.2 Analog In to S/PDIF or PSIA Out ...................................................................................................... 9
4. SOFTWARE MODE CONTROL .......................................................................................................... . 10
4.1 Board Configuration Tab ................................................................................................................ 11
4.2 CODEC Configuration Tab ............................................................................................................. 12
4.3 Analog Input Volume Tab ............................................................................................................... 13
4.4 DSP Engine Tab ............................................................................................................................. 14
4.5 Analog Output Volume Tab ............................................................................................................ 15
4.6 Register Maps Tab ......................................................................................................................... 16
5. SYSTEM CONNECTIONS AND JUMPERS ........................................................................................ 17
6. PERFORMANCE PLOTS ..................................................................................................................... 19
7. CDB42L55 BLOCK DIAGRAM ............................................................................................................ 24
8. CDB42L55 SCHEMATICS ................................................................................................................... 25
9. CDB42L55 LAYOUT ............................................................................................................................ 30
10. REVISION HISTORY .......................................................................................................................... 35