Cirrus Logic CDB4244 - Manual (Page 2)

2 DS900DB2
CDB4244
TABLE OF CONTENTS
1 SYSTEM OVERVIEW .............................................................................................................................. 4
1.1 Power ............................................................................................................................................... 4
1.2 Grounding and Power Supply Decoupling ....................................................................................... 4
1.3 CS4244 Multi-Channel CODEC ....................................................................................................... 4
1.4 CS8406 Digital Audio Transmitter .................................................................................................... 4
1.5 CS8416 Digital Audio Receiver ........................................................................................................ 5
1.6 CS2000 Fractional-N Clock Synthesizer & Clock Multiplier ............................................................. 5
1.7 Oscillator .......................................................................................................................................... 5
1.8 External Connection Headers .......................................................................................................... 5
1.9 Analog Inputs ................................................................................................................................... 6
1.10 Analog Outputs .............................................................................................................................. 6
2 SOFTWARE MODE CONTROL .............................................................................................................. 7
2.1 Board Control Tab ............................................................................................................................ 8
2.2 CODEC Control Tab ........................................................................................................................ 9
2.3 Volume Control Tab ....................................................................................................................... 10
2.4 Register Maps Tab ......................................................................................................................... 11
2.5 Predefined Sample Scripts ............................................................................................................ 12
3 MASTER CLOCK CONFIGURATION ................................................................................................... 13
3.1 CS8416 Recovered Master Clock .................................................................................................. 13
3.2 CS2000-Generated Master Clock .................................................................................................. 14
3.3 CS2000 Timing Reference ............................................................................................................. 14
3.4 Miscellaneous Options ................................................................................................................... 14
4 ANALOG INPUT FILTERS .................................................................................................................... 15
4.1 Active Single-Ended-to-Differential Input Filter .............................................................................. 15
4.2 Passive Differential Input Filter ...................................................................................................... 15
4.3 Analog Input Filter Configuration ................................................................................................... 16
5 ANALOG OUTPUT FILTERS ................................................................................................................ 17
5.1 Analog Output Filter Considerations .............................................................................................. 17
5.2 Analog Output Filter Configuration ................................................................................................. 19
6 SYSTEM CONNECTIONS AND JUMPER PIN BLOCKS ..................................................................... 20
6.1 System Connections ...................................................................................................................... 20
6.2 Jumper Pin Blocks ......................................................................................................................... 21
6.3 Test Points ..................................................................................................................................... 21
7 CDB4244 BLOCK DIAGRAM ............................................................................................................... 22
8 CDB4244 SCHEMATIC ......................................................................................................................... 23
9 CDB4244 LAYOUT ................................................................................................................................ 31
10 REVISION HISTORY ........................................................................................................................... 36
LIST OF FIGURES
Figure 1.Board Control Tab ......................................................................................................................... 8
Figure 2.CODEC Control Tab ..................................................................................................................... 9
Figure 3.Volume Control Tab .................................................................................................................... 10
Figure 4.Register Maps Tab ...................................................................................................................... 11
Figure 5.Master Clock Path ....................................................................................................................... 13
Figure 6.Active Single-Ended-to-Differential Input Filter Block Diagram ................................................... 15
Figure 7.Passive Differential Input Filter Block Diagram ........................................................................... 15
Figure 8.Analog Output Filter Block Diagram ............................................................................................ 17
Figure 9.CDB4244 Block Diagram ............................................................................................................ 22
Figure 10.CS4244 (Schematic Sheet 1) ................................................................................................... 23
Figure 11.S/PDIF I/O (Schematic Sheet 2) ............................................................................................... 24
Figure 12.USB I/O (Schematic Sheet 3) ................................................................................................... 25
Figure 13.Analog Input Channels 1 & 2 (Schematic Sheet 4) ................................................................... 26