Cirrus Logic CDB4244 - Manual (Page 14)

14 DS900DB2
CDB4244
3.2 CS2000-Generated Master Clock
For greater flexibility, the CS2000 can be configured to provide a master clock at several different frequen-
cies. This eliminates the need to replace the socketed oscillator to achieve different sample rates in the
event that the incoming S/PDIF stream is unavailable. Note that either the CS4244 or CS8406 must be con-
figured as master in order to achieve different sample rates using the master clock generated by the
CS2000. The CS8416 must be configured as slave or disabled to prevent contention on the LRCK and
SCLK signals (refer to the CS8416 data sheet for more information). It is not recommended to exercise the
digital-input-to-analog-output path (through the CS8416 and the CS4244 DACs) while the CS8416 is con-
figured as slave, because the sample rate delivered to the CS8416 OLRCK input and the sample rate from
the incoming S/PDIF stream are generated in two different clock domains. This may result in repeated or
dropped samples, distorting the analog output signal produced by the CS4244.
Different master clock frequencies are realized by choosing one of the “CS2000 Generated...” options within
the “CS4244 and CS8406 MCLK Source” menu in the “Board Control” tab of the FlexGUI software. Each
option shows the master clock frequency, anticipated master-clock-to-sample-rate ratio, and the resulting
sample rate. For example, “12.2880 MHz (256x48.0 kHz)” means that a sample rate of 48.0 kHz with an
MCLK / F
S
ratio equal to 256 results in a 12.2880-MHz master clock.
A total of 18 common master clock frequencies that are supported by the CS4244 are provided. It is the
user’s responsibility to ensure that the CS4244 is configured to accept the incoming master clock by making
the appropriate changes in the “CODEC Control” tab of the FlexGUI software. See
Section 2.2 on page 9
and the CS4244 data sheet for more information. Furthermore, the user must also ensure that the CS8406
is properly configured to match the relevant serial port settings of the CS4244 by making the appropriate
changes in the “Board Control” tab (refer to the CS8406 data sheet for more information). Note that not all
of the master-clock-to-sample-rate ratios that are supported by the CS4244 are supported by the CS8406.
The remaining CS4244 combinations may only be exercised through external control (refer to
Section 1.8
on page 5 ).
3.3 CS2000 Timing Reference
By default, the CS2000 uses a 16-MHz crystal to serve as the device’s timing reference. Alternatively, this
crystal can be removed so that the socketed 12.2880-MHz oscillator serves as the device’s timing refer-
ence. This is accomplished by first removing the crystal (Y1) and capacitors C34 and C35, and then popu-
lating R24 with a 0-
Ω 0603 SMT resistor. This routes the oscillator to the CS2000 timing reference clock
input pin.
Note: The FlexGUI software and associated scripts assume the use of a 16-MHz timing reference.
Changes to this frequency will alter the frequencies generated by the “CS2000 Generated...” op-
tions within the “CS4244 and CS8406 MCLK Source” menu. Furthermore, using a timing reference
frequency other than that of the default 16-MHz crystal may require changes to the Reference
Clock Input Divider register setting of the CS2000. Therefore, it is highly recommended that the
crystal timing reference is not altered from its factory preset configuration. Refer to the CS2000
data sheet for more information.
3.4 Miscellaneous Options
The clock present on the timing reference pin of the CS2000 can act as the system master clock by selecting
“External Timing Reference” under the “CS4244 and CS8406 MCLK Source” menu. Alternatively, the mas-
ter clock can be disabled by selecting “OFF” from the same menu. This configures the auxiliary output of
the CS2000 as high impedance.