Cirrus Logic CDB4244 - Manual (Page 13)

DS900DB2 13
CDB4244
3 MASTER CLOCK CONFIGURATION
The CDB4244 offers many options for generating a system master clock. The master clock can be recovered from
the incoming S/PDIF stream by the S/PDIF receiver or sourced from the socketed onboard oscillator in the event
that the S/PDIF receiver’s internal PLL becomes unlocked. This clock can be passed directly to the CS4244 and
CS8406, or it can be passed through the CS2000 first to reduce jitter. Alternatively, the CS2000 can be used to gen-
erate a system master clock based on the onboard 16-MHz crystal. This option can be used to exercise 18 common
master clock and sampling frequency combinations supported by the CS4244. Each of these options can be quickly
realized using the FlexGUI software, with no change in hardware required.
Figure 5 highlights how these compo-
nents work together.
Figure 5. Master Clock Path
Note that the CS8416 S/PDIF receiver and the CS2000 are the only devices on the CDB4244 that can provide a
system master clock. However, the S/PDIF receiver, S/PDIF transmitter, and CODEC are all capable of mastering
system timing under the I²S and Left-Justified serial interface formats. Each device can be configured as master or
slave using the FlexGUI software. It is the user’s responsibility to ensure that only one device serves as master, with
the remaining devices configured as slaves.
3.1 CS8416 Recovered Master Clock
By default, the master clock presented to the CS4244 and CS8406 is generated by the delta-sigma fraction-
al-N frequency synthesizer of the CS2000. This low-jitter clock source is matched in frequency to the master
clock recovered by the CS8416. The FlexGUI software enables this option at startup. This configuration can
be restored by selecting the “CS8416 Recovered MCLK (Clean)” option under the “CS4244 and CS8406
MCLK Source” menu in the “Board Control” tab (see
Section 2.1 on page 8 for more information).
In the event that the CS8416’s internal PLL becomes unlocked, the CS8416 automatically sources the mas-
ter clock from the socketed oscillator. This assumes the “Auto Clock Switching” box in the “CS8416 S/PDIF
Receiver” group is checked. In this case, different master clock frequencies (and hence different sample
rates) can be realized by replacing the socketed oscillator with oscillators of different frequencies.
Alternatively, the master clock recovered by the CS8416 can be passed directly to the CS4244 and CS8406
by choosing the “CS8416 Recovered MCLK (Raw)” option under the “CS4244 and CS8406 MCLK Source”
menu. In this configuration, no jitter reduction is performed on the master clock presented to the CS4244
and CS8406. The CS2000 can be physically eliminated from the clocking path by removing all components
pertaining to the CS2000 (U3, R25, C32, C33, C34, C35, Y1), and then populating R20 with a 0-
Ω 0603
SMT resistor. Note that under this configuration, the “CS4244 and CS8406 MCLK Source” menu in the
FlexGUI software has no effect.
CS8416 CS2000
Osc.
CS4244
S/PDIF IN
CS8406
RMCK MCLK
OMCK
OMCK
S/PDIF OUT
AUX_OUT CLK_IN
Crystal