Cirrus Logic AN241 - Manual (Page 14)

AN241
14
Figure 7. Single Ended Input Buffer with a Common Reference Pin
5.4 Overview of Filter Topology
5.4.1 High Pass Filter and DC Biasing
The first stage of the buffer forms a high pass filter from the combination of the AC-coupling capacitor
along with the resistor divider that biases the positive terminal of the op-amps to the proper DC bias volt-
age. The value of the resistors denoted as “R” will vary depending on the optimal DC bias for the given
converter. Typically this is around half of the VA voltage supply. Please refer to the converter datasheet
for the recommended input bias voltage. The 3dB corner of the high pass filter can be calculated as fol-
lows:
where: R
EQ
is the value of the resistor divider in parallel (in Ohms)
C is the value of the AC-coupling capacitor (in Farads)
AINL
VCOM
or V Q
-
+
470 pF
C0G
CSxxxx
634 Ω
91 Ω
2700 pF
C0G
4.7 µF
R kΩ
1 µF 0.01 µF
AINR
2700 pF
C0G
-
+
470 pF
C0G
91 Ω
634 Ω
100 kΩ
100 kΩ
VA
4.7 µF
R kΩ 100 kΩ
100 kΩ
VA
C R
F
EQ
C π
2
1
=