An241 – Cirrus Logic AN241 User Manual
Page 10
AN241
10
4.6
Overview of Filter Topology #2
4.6.1
High Pass Filter and DC Biasing
The first stage of the buffer forms a high pass filter from the combination of the AC-coupling capacitor
along with the resistor divider that biases the positive terminal of the op-amp to the proper DC bias volt-
age. The value of the resistors denoted as “R” will vary depending on the optimal DC bias for the given
converter. Typically this is around half of the VA voltage supply. A high pass filter is also formed from the
resistor divider and capacitor to ground on the reference voltage pin of each channel. The 3dB corner of
the high pass filter can be calculated as follows:
where:
R
EQ
is the value of the resistor divider in parallel (in Ohms)
C
is the value of the capacitor (in Farads)
In the input buffer shown in Figure 5,
R
EQ
≈
50 k
Ω
(100 k
Ω
R k
Ω
) and
C
= 4.7
µ
F. This places the 3 dB
corner at approximately 0.68 Hz. Typically, this corner should be at least one decade below the bandwidth
of interest in order to prevent a significant droop in the frequency response.
Since the input impedance into the op-amp is extremely high, the effective input impedance into the ana-
log input buffer will be determined by the parallel combination of the resistors in the biasing divider in par-
allel with the 100 k
Ω
shunt resistor. In the input buffer shown above, the input impedance is approximately
33 k
Ω.
Ideally, the larger this input impedance the better. However, in the input buffer shown in Figure 5,
the AC-coupling capacitor will initially be charged up via the resistor divider. This charge up time is de-
pendent on the size of the AC-coupling capacitor and the amount of resistance to the VA voltage supply.
The time constant can be calculated as follows:
where
R
EQ
= the amount of resistance between the AC-coupling capacitor and the voltage supply (in
Ohms)
C
= the value of capacitance of the AC-coupling capacitor (in Farads)
In the input buffer shown in Figure 5,
R
EQ
≈
50 k
Ω
(100 k
Ω
R k
Ω
), and
C
= 4.7
µ
F. This produces a
time constant of approximately 0.24 s. This would indicate that the capacitor will charge up to within 99%
of the final DC value in approximately 1. 2s (which is 5 time constants). The 10 0k
Ω
resistors to ground
on the input node allow a DC path to charge the AC-coupling capacitor, regardless of whether or not there
is an input signal source present.
4.6.2
Op Amp Circuitry and Anti-Aliasing Capacitor
The op-amp topology used in the input buffer shown in Figure 5 addresses two issues. First, it provides
an extremely low output impedance and therefore minimizes the amount of distortion presented to the
converters internal sampling circuits. By placing the 91
Ω
resistor in the feedback loop, it’s resistance is
divided by the open-loop gain of the op-amp, providing a sub-ohm output impedance. Secondly, this op-
amp topology provides a low pass filter. Using the recommended values, this filter remains flat throughout
the audio passband and provides approximately 2 0dB of rejection at the modulator sampling rate (where
C
R
F
EQ
C
π
2
1
=
C
R
EQ
=
τ