An241 – Cirrus Logic AN241 User Manual

Page 12

AN241

4.8

Overview of Filter Topology #3

4.8.1

Op Amp Circuitry

The op-amp topology used in the input buffer shown in Figure 6 addresses two issues. First, it provides
an extremely low output impedance and therefore minimizes the amount of distortion presented to the
converters internal sampling circuits. By placing the 91

Ω

resistor in the feedback loop, it’s resistance is

divided by the open-loop gain of the op-amp, providing a sub-ohm output impedance (not including the
ESR of the AC-coupling capacitor). Secondly, this op-amp topology provides a low pass filter. Using the
recommended values, this filter remains flat throughout the audio passband and provides approximately
20 dB of rejection at the modulator sampling rate (where the converter is susceptible to aliasing). The
characteristics of this low pass filter can be changed by adjusting the values of the resistors and capaci-
tors in the feedback loop. However, it is important to maintain a flat frequency response throughout the
passband of interest and to provide reasonable attenuation at the input sampling rate of the converter.
Also, low value resistors should be used to minimize the addition of resistor thermal noise.

4.8.2

High Pass Filter and DC Biasing

The outputs of the op-amps are AC-coupled to the converter, with the converter inputs being biased to
the proper voltage level through a 10 k

Ω

resistor from the DC-biasing op-amp. The AC-coupling capacitor

and resistor from the biasing op-amp form a high pass filter. The 3 dB corner of the high pass filter can be
calculated as follows:

where:

is the value of the resistor to the biasing op-amp (in Ohms)

is the value of the AC-coupling capacitor (in Farads)

In the input buffer shown in Figure 6,

= 10 k

Ω

and

= 470

F. This places the 3 dB corner at approxi-

mately 0.03 Hz. Typically, this corner should be at least one decade below the bandwidth of interest in
order to prevent a significant droop in the frequency response. The value of the AC-coupling capacitor
must be large in order to prevent the DC resistance of the capacitor from degrading signal linearity. Please
note that with 470

F aluminum electrolytic capacitors, distortion will begin to increase at input frequen-

cies below 100 Hz.

In Figure 6, the AC-coupling capacitor will initially be charged up via the op-amp connected to the on-chip
voltage reference. This charge up time is dependent on the size of the AC-coupling capacitor and the
amount of series resistance to the op-amp. The time constant can be calculated as follows:

where

= the amount of resistance between the AC-coupling capacitor and the op-amp (in Ohms)

= the value of capacitance of the AC-coupling capacitor (in Farads)

In the input buffer shown in Figure 6,

= 10 k

Ω

, and

= 470

F. This produces a time constant of ap-

proximately 4.7 s. This would indicate that the capacitor will charge up to within 99% of the final DC value
in approximately 23.5 s (which is 5 time constants).