Cirrus Logic CS2100-CP - Manual (Page 10)

CS2100-CP
10 DS840F2
CONTROL PORT SWITCHING CHARACTERISTICS - SPI FORMAT
Inputs: Logic 0 = GND; Logic 1 = VD; C
L
= 20 pF.
Notes: 13. t
spi
is only needed before first falling edge of CS after power is applied. t
spi
= 0 at all other times.
14. Data must be held for sufficient time to bridge the transition time of CCLK.
15. For f
cclk
< 1 MHz.
Parameter Symbol Min Max Unit
CCLK Clock Frequency f
ccllk
- 6 MHz
CCLK Edge to CS Falling ( Note 13 ) t
spi
500 - ns
CS High Time Between Transmissions t
csh
1.0 - µs
CS Falling to CCLK Edge t
css
20 - ns
CCLK Low Time t
scl
66 - ns
CCLK High Time t
sch
66 - ns
CDIN to CCLK Rising Setup Time t
dsu
40 - ns
CCLK Rising to DATA Hold Time ( Note 14 ) t
dh
15 - ns
Rise Time of CCLK and CDIN ( Note 15 ) t
r2
- 100 ns
Fall Time of CCLK and CDIN ( Note 15 ) t
f2
- 100 ns
Delay from Supply Voltage Stable to Control Port Ready t
dpor
100 - µs
t
r2
t
f2
t
dsu
t
dh
t
sch
t
scl
CS
CCLK
CDIN
t
css t
csh
t
spi
t
dpor
VD
Figure 6. Control Port Timing - SPI Format (Write Only)