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7 function configuration 2 (address 17h), 1 enable pll clock output on unlock (clkoutunl), 2 low-frequency ratio configuration (lfratiocfg) – Cirrus Logic CS2100-CP User Manual

Page 29: 8 function configuration 3 (address 1eh), 1 clock input bandwidth (clkin_bw[2:0]), P 29, Cs2100-cp

7 function configuration 2 (address 17h), 1 enable pll clock output on unlock (clkoutunl), 2 low-frequency ratio configuration (lfratiocfg) | 8 function configuration 3 (address 1eh), 1 clock input bandwidth (clkin_bw[2:0]), P 29, Cs2100-cp | Cirrus Logic CS2100-CP User Manual | Page 29 / 32 7 function configuration 2 (address 17h), 1 enable pll clock output on unlock (clkoutunl), 2 low-frequency ratio configuration (lfratiocfg) | 8 function configuration 3 (address 1eh), 1 clock input bandwidth (clkin_bw[2:0]), P 29, Cs2100-cp | Cirrus Logic CS2100-CP User Manual | Page 29 / 32
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