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6 function configuration 1 (address 16h), 1 clock skip enable (clkskipen), 2 aux pll lock output configuration (auxlockcfg) – Cirrus Logic CS2100-CP User Manual

Page 28: 3 reference clock input divider (refclkdiv[1:0]), P 28, Aux pll lock output config, Cs2100-cp

6 function configuration 1 (address 16h), 1 clock skip enable (clkskipen), 2 aux pll lock output configuration (auxlockcfg) | 3 reference clock input divider (refclkdiv[1:0]), P 28, Aux pll lock output config, Cs2100-cp | Cirrus Logic CS2100-CP User Manual | Page 28 / 32 6 function configuration 1 (address 16h), 1 clock skip enable (clkskipen), 2 aux pll lock output configuration (auxlockcfg) | 3 reference clock input divider (refclkdiv[1:0]), P 28, Aux pll lock output config, Cs2100-cp | Cirrus Logic CS2100-CP User Manual | Page 28 / 32
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