Elitegroup Z87H3-AX GOLDEN (V1.0) - Manual (Page 52)

Chapter 3
Z87H3-AX EXTREME (GOLDEN) USER MANUAL
46
Intel(R) Thunderbolt
The items in this menu allows you to configure Intel(R) Thunderbolt settings.
Security level selection.
Main Advanced Chipset M.I.B. X Boot Security Exit
+/- : Change Opt.
Enter/Dbl Click : Select


: Select Screen
/Click: Select Item
F1: General Help
F2: Previous Values
F3: Optimized Defaults
F4: Save & Exit
ESC/Right Click: Exit
Thunderbolt Host Chip (Redwood Ridge)
This item shows the thunderbolt Host chip type.
Thunderbolt Specification Version (0.9)
This item shows the thunderbolt specification version.
Intel Sample Code Version (1.5)
This item shows the Intel sample code version.
Security Level (Legacy Mode)
Use this item to select the security level.
Wake From Thunderbolt Devices (Enabled)
Use this item to enable or disable system wake from thunderbolt devices.
Thunderbolt PCIe Cache-line Size (32)
This item allows you to configure cache-line size value to be configured on
thunderbolt PCIe subtree.
SMI/Notify Support (Enabled)
This item allows you to enable or disable SMI/Notify support.
Notify Support (Enabled)
This item allows you to enable or disable Notify support in ASL code.
Thunderbolt Surprise-Removal (Disabled)
This item allows you to enable or disable thunderbolt surprise removal
workaround support.
SwSMI Support (Enabled)
This item allows you to enable or disable SwSMI support in ASL code.
Intel(R) Thunderbolt Configuration
Thunderbolt Specification Version
0.9
Intel Sample Code Version 1.5
Thunderbolt Host Chip Redwood Ridge
Security Level Legacy Mode
Wake From Thundebolt Devices Enabled
Thunderbolt PCIe Cache-line Size 32
SMI/Notify Support Enabled
SwSMI Support Enabled
Notify Support Enabled
Thunderbolt Surprise-Removal Disabled
Ignore Thunderbolt Option Rom Enabled
Thunderbolt SwSMI Delay 0
Reserved Mem per phy slot 32
Reserved PMem per phy slot 32
TBT Device IO resource Support Disabled