Teledyne LeCroy QPHY-MIPI-DPHY - Manual (Page 25)

QPHY-MIPI-DPHY Software Option
918841 Rev A
25
A Lane enters the Reverse High-Speed Data Transmission mode by means of a Link Turnaround procedure as
specified in section 5.5. Reverse Data Transmission is not source-synchronous; the Clock signal is driven by the
Master side while the Data Lane is driven by the Slave side. The Slave Side transmitter shall send one data bit
every two periods of the received Clock signal. Therefore, for a given Clock frequency, the Reverse direction data
rate is one-fourth the Forward direction data rate. The bit period in this case is defined to be 4*UI
INST
. UI
INST
is the
value specified for the full-rate forward transmission.
DUT UI inst minimum value
This variable allows the user to specify the minimum instantaneous UI possible within a High-Speed data transfer
for a given implementation. This value must be obtained from the DUT vendor. The default value is 1e-9.