beautypg.com

Digital modulation – Atec Rohde-Schwarz-SMIQ Series User Manual

Page 8

background image

8

Vector Signal Generator R&S SMIQ – Specifications

Digital modulation

Digital modulation with optional Modulation Coder R&S SMIQB20

Modes

internal, external serial, external parallel

Predefined modulation settings

APCO C4FM, APCO CQPSK, CDPD, CT2, DECT, GSM, IRIDIUM,
NADC, PDC, PHS, TETRA, TFTS, PWT, ICO BPSK, ICO GMSK,
ICO QPSK, GSM EDGE, CDMA IS-95, WCDMA, QPSK

Internal PRBS

selectable lengths: 2

9

−1, 2

15

−1, 2

16

−1, 2

20

−1, 2

21

−1 and 2

23

−1

I/Q bandwidth

12 MHz

Modulation specifications apply at levels

≤8 dBm (PEP) with R&S SMIQ02B/03B and at levels ≤5 dBm (PEP) with

R&S SMIQ04B/06B
Total level uncertainty at levels >

−127 dBm with

digital modulation, crest factor <20 dB

2) 3)

f

≤2,5 GHz

f >2,5 GHz to 4 GHz
f >4 GHz

<0.7 dB
<1.2 dB
<1.5 dB

For best short time repeatability use ALL OFF mode table
Clock generation

Clock mode
Resolution
Error

internal or external
0.001 Hz
<2

−42

, related to reference frequency

Inputs

DATA, BIT CLOCK, SYMBOL CLOCK, PAR DATA

Serial data are taken from BNC connectors, parallel data (symbols) from rear PAR DATA connector. Parallel symbols may
contain 1 to 8 bits and read in using an internal or external clock signal
Trigger threshold
Input impedance
Max. data rate, serial
Max. symbol rate, parallel

−2.5 V to +2.5 V, selectable, resolution 0.01 V
1 k

Ω to ground, 50 Ω to ground

30 MHz, 50 MHz typ.
18 MHz

Outputs
I and Q baseband signals, output voltage, EMF,
peak value
Power ramp

Output voltage
Output impedance

DATA, BIT CLOCK, SYMBOL CLOCK, PAR DATA, (all TTL levels)

0 V to 1 V
10

Level attenuation
via LEV ATT input
Range
Additional level error caused by attenuation

3 )

0 dB to 70 dB
<1 dB (up to 35 dB), <1.5 dB (up to 70 dB)

Envelope control
Modes

Analog

External via POWER RAMP input (for data see vector modulation
above). With an internal power ramp, the connector serves as an output.

Digital

Internal or external via BURST GATE input/output (PAR DATA connec-
tor). The BURST GATE input triggers a power ramp (TTL levels). The
low/high transition starts the ramp function from blanking level to max-
imum level, the high/low transition from maximum level to blanking
level. With an internal power ramp, the connector serves as an output.

Operating range

1 kHz to 2.5 MHz

Rise/fall time

Setting range
Resolution
Minimum time

0.25 symbols to 32 symbols
1/4 symbol
1 µs

Modulation modes

ASK, FSK, GMSK, PSK, QAM

I

2

Q

2

+

1V

=