Ocean Optics External Triggering Options Instructions for Spectrometers with Firmware Version 3.0 and Above - Manual (Page 5)

External Triggering Instructions for FW 3.0 and Above
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Note
Once you select an external trigger mode, your computer will appear unresponsive. This
is normal, as the computer is waiting for a trigger. You must apply one more trigger to
the spectrometer after selecting a new trigger mode.
External Triggering vs. Triggering an External
Event
There could be some confusion between the concepts of External Triggering and triggering an external
event. The following sections explain each of these concepts:
• External Triggering – An event outside the sampling system (such as a push button, lever
activation, or laser pulse) triggers the voltage level on the spectrometer’s trigger pin and instructs
the spectrometer to begin spectra acquisition.
• Triggering an External Event – When triggering an external event, the spectrometer instructs an
external device (typically a lamp such as the PX-2 or the LS-450) to illuminate immediately prior
to spectral acquisition.
Trigger Mode Descriptions
The following sections specify the Trigger modes for Ocean Optics spectrometers with firmware versions
3.0 and above and associated timing sequences.
For the Maya2000Pro, HR2000+and USB2000+ and USB4000, the timing sequences specified are for the
trigger mechanism interacting with a single-depth FIFO. The hardware implementing these Trigger
modes may enhance the capability and performance by implementing buffering schemes using larger or
multiple FIFOs.
For the QE65000, the timing sequences specified are for the trigger mechanism interacting with a triple-
depth FIFO. The hardware implementing these Trigger modes enhances the capability and performance
by implementing a buffering scheme using multiple FIFOs.
Normal Mode
In the Normal (Free-run) mode, the spectrometer will acquire back-to-back spectra based on the
integration period specified. After the Integration Cycle completes, the data is read out of the detector
and written into an internal FIFO where it is available for reading. In parallel to this read/write operation,
another integration is occurring. If the data from the FIFO is completely read before the parallel
integration completes, a back-to-back operation will occur. If the data is not read (FIFO Empty) in this
time period, the FPGA will generate an Idle Cycle which is equivalent to one integration period and the
data from the detector is discarded. After the Idle Cycle has completed, the FIFO Empty status is