Ocean Optics External Triggering Options Instructions for Spectrometers with Firmware Version 3.0 and Above - Manual (Page 11)

External Triggering Instructions for FW 3.0 and Above
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External Hardware Edge Trigger Mode
In the External Hardware Edge Trigger mode, a rising edge detected by the FPGA from the External
Trigger input starts the Integration Cycle specified through the software interface. After the Integration
Cycle completes, the spectrum is retrieved and written to the FIFO in the FPGA followed by a CCD Reset
Cycle. Only one acquisition will be performed for each External Trigger pulse, no matter what the
pulse’s duration is. The Reset Cycle insures that the CCD performance uniform on a scan-to-scan basis.
The time duration for this reset cycle is relative to the Integration Cycle time and will change if the
integration period is changed. So the timing sequence is Trigger, Trigger Delay, Integration Cycle,
Read/Write Cycle, Reset Cycle, and Idle Cycle(s). The Idle Cycle will until the next trigger occurs.
Note
For the QE Pro, jitter between external edge trigger and start of column binning (or
trigger delay) is 40ns.
Maya2000Pro and QE65000 Hardware Edge Trigger Mode Time Table