Rainbow Electronics MAX1855 - Manual (Page 26)

MAX1716/MAX1854/MAX1855
High-Speed, Adjustable, Synchronous Step-Down
Controllers with Integrated Voltage Positioning
26 ______________________________________________________________________________________
________________Applications Issues
Voltage Positioning and
Effective Efficiency
Powering new mobile processors requires careful
attention to detail to reduce cost, size, and power dissi-
pation. As CPUs became more power hungry, it was
recognized that even the fastest DC-DC converters
were inadequate to handle the transient power require-
ments. After a load transient, the output instantly
changes by ESR
COUT
× ∆I
LOAD
. Conventional DC-DC
converters respond by regulating the output voltage
back to its nominal state after the load transient occurs
(Figure 7). However, the CPU only requires that the out-
put voltage remain above a specified minimum value.
Dynamically positioning the output voltage to this lower
limit allows the use of fewer output capacitors and
reduces power consumption under load.
For a conventional (nonvoltage-positioned) circuit, the
total voltage change is:
V
P-P1
= 2 × (ESR
COUT
× ∆I
LOAD
) + V
SAG
+ V
SOAR
where V SAG and V SOAR are defined in Figure 8. Setting
the converter to regulate at a lower voltage when under
load allows a larger voltage step when the output cur-
rent suddenly decreases (Figure 7). So the total voltage
change for a voltage positioned circuit is:
V P-P2 = (ESR COUT
× ∆I
LOAD ) + V SAG + V SOAR
where V SAG and V SOAR are defined in the Design
Procedure. Since the amplitudes are the same for both
circuits (V
P-P1
= V
P-P2
), the voltage-positioned circuit
requires only twice the ESR. Since the ESR specifica-
tion is achieved by paralleling several capacitors, fewer
units are needed for the voltage-positioned circuit.
An additional benefit of voltage positioning is reduced
power consumption at high load currents. Because the
output voltage is lower under load, the CPU draws less
current. The result is lower power dissipation in the
CPU, although some extra power is dissipated in
R
SENSE . For a nominal 1.6V, 18A output (R LOAD =
89m
Ω), reducing the output voltage 2.9% gives an out-
put voltage of 1.55V and an output current of 17.44A.
Given these values, CPU power consumption is
reduced from 28.8W to 27.03W. The additional power
consumption of R
SENSE is:
2.5m
Ω × (17.44A) 2 = 0.76W
and the overall power savings is as follows:
28.8W - (27.03W + 0.76W) = 1.01W
In effect, 1.8W of CPU dissipation is saved and the
power supply dissipates much of the savings, but both
the net savings and the transfer of heat away from the
CPU are beneficial. Effective efficiency is defined as
the efficiency required of a nonvoltage-positioned cir-
cuit to equal the total dissipation of a voltage-posi-
tioned circuit for a given CPU operating condition.
Calculate effective efficiency as follows:
1) Start with the efficiency data for the positioned
circuit (V IN , I IN , V OUT , I OUT ).
2) Model the load resistance for each data point:
I LOAD
CAPACITOR SOAR
(ENERGY IN L
TRANSFERRED TO C
OUT
)
CAPACITIVE SAG
(dV/dt = I
OUT
/C
OUT
)
RECOVERY
ESR STEP-DOWN
AND STEP-UP
(I STEP X ESR)
V OUT
Figure 8. Transient-Response Regions
B
1.6V
1.6V
A
A. CONVENTIONAL CONVERTER (50mV/div)
B. VOLTAGE POSITIONED OUTPUT (50mV/div)
VOLTAGE POSITIONING THE OUTPUT
MAX1716-Figure 07
Figure 7. Voltage Positioning the Output