Rainbow Electronics MAX1168 - Manual (Page 21)

are shut down on the EOC high-to-low transition. Use
the EOC high-to-low transition as the signal to restart
the external clock (SCLK). To read the entire conver-
sion result, 16 SCLK cycles are needed. Extra clock
pulses, occurring after the conversion result has been
clocked out and prior to the rising edge of CS, cause
the conversion result to be shifted out again. The
MAX1168 internal-clock 16-bit-wide data-transfer mode
requires 32 external clock cycles and 32 internal clock
cycles for completion. Force CS high after the conversion result is read. For
maximum throughput, force CS low again to initiate the
next conversion immediately after the specified mini-
mum time (t
CSW ). Forcing CS high in the middle of a
conversion immediately aborts the conversion and
places the MAX1168 in shutdown.
Scan mode allows multiple channels to be scanned
consecutively or one channel to be scanned eight
times. Scan mode can only be enabled when using the
MAX1168 in internal clock mode. Enable scanning by
MAX1167/MAX1168
Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
______________________________________________________________________________________ 21
DOUT
CS
DSPR
SCLK
DIN
DSPX
0
MSB LSB
MSB LSB
t ACQ IDLE t CONV
ADC
STATE
1 8 16 24
Figure 17. DSP External Clock Mode, 8-Bit Data-Transfer Mode, Conversion Timing (MAX1168 Only)
DOUT
CS
SCLK
DIN 0
MSB LSB
MSB LSB
ADC
STATE
16 24 32 1 8
X X X X X X X X
X = DON
,
T CARE
t ACQ IDLE t CONV
DSPR
DSPX
Figure 18. DSP External Clock Mode, 16-Bit Data-Transfer Mode, Conversion Timing (MAX1168 Only)