Rainbow Electronics MAX8514 - Manual (Page 17)

MAX8513/MAX8514
Wide-Input, High-Frequency, Triple-Output Supplies
with Voltage Monitor and Power-On Reset
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Internal 5V Linear Regulator
All MAX8513/MAX8514 functions (except for the posi-
tive output LDO with an NFET or NPN, and the negative
LDO on the MAX8514) are powered from the on-chip
low-dropout 5V regulator with its input connected to IN.
Bypass the regulator’s output (VL) with a 2.2µF or
greater ceramic capacitor. The V
IN
to V
VL
dropout volt-
age is typically 350mV, so when V IN is greater than
5.5V, V VL is typically 5V. If V IN is between 4.5V and
5.5V, short VL to IN.
Undervoltage Lockout
If V VL drops below 3.8V, the MAX8513/MAX8514
assume that the supply voltage is too low to make valid
decisions. When this happens, the undervoltage lock-
out (UVLO) circuitry inhibits switching, forces POR and
PFO low, and forces DL and DH gate drivers low. After
V
VL rises above 3.9V, the controller powers up the out-
puts (see the Startup section).
Startup
The MAX8513/MAX8514 start switching when V VL rises
above the 3.9V UVLO threshold. However, the con-
troller is not enabled unless all three of the following
conditions are met:
1) V VL exceeds the 3.9V UVLO threshold.
2) The internal reference exceeds 90% of its nominal
value.
3) The thermal limit is not exceeded.
Once the MAX8513/MAX8514 assert the internal enable
signal, the step-down controller starts switching and
enables soft-start. The soft-start circuitry gradually ramps
up to the reference voltage to control the rate-of-rise of
the step-down controller and reduce input surge cur-
rents. The soft-start period is determined by the value of
the capacitor from SS to GND (C13 in the Typical
Applications Circuits). SS sources a constant 25µA to
charge the soft-start capacitor to 1.25V.
Output-Voltage Sequencing
The MAX8513/MAX8514 can power up in either stag-
gered-output sequencing or output tracking. For stag-
gered-output sequencing, connect SEQ to GND. In this
configuration, V
OUT1 comes up first. When it reaches
90% of the nominal regulated value, V OUT2 is softly
turned on. Once V OUT2 reaches 90% of its nominal regu-
lated value, V OUT3 is softly turned on. Individual soft-start
on OUT2 and OUT3 eliminates glitches on the previous
stages due to the charging of output capacitors. See the
Typical Operating Characteristics section for the startup
and staggered-output-sequence waveforms.
Output-Voltage Tracking
When SEQ is connected to VL, all outputs rise up at the
same time and the external series pass transistors are
driven fully on until reaching the respective regulation
limits. Since the LDOs are powered from the main DC-
DC step-down converter, either directly or through a
coupled winding on the inductor, their outputs track the
DC-DC step-down output (OUT1). See the Typical
Operating Characteristics section for the startup output-
tracking waveforms.
Power-On Reset
The MAX8513/MAX8514 provide a power-on-reset (POR)
signal, which goes high 315ms after all outputs reach
90% of their nominal regulated value. Therefore, by the
time POR goes high, all outputs are already stabilized at
nominal regulated voltages. See the Typical Operating
Characteristics section for the POR waveforms.
Input Power-Fail (PFI and PFO)
The MAX8513/MAX8514 have a built-in comparator to
detect the input voltage with an external resistive-
divider at PFI, with a threshold of 1.22V. When the input
voltage drops and trips this comparator, the power-fail
output (PFO) goes low, while all outputs are still within
regulation limits. This is typically used for input power-
fail warning for orderly system shutdown. The amount of
warning time depends on the input storage capacitor,
the input PFI trip voltage level, the main step-down out-
put voltage, the total output power, and the efficiency.
See the Design Procedure section for how to calculate
the input capacitor to meet the required warning time.
Enable and Synchronization
The MAX8513/MAX8514 can be turned on with logic
high, and off with logic low at SYNC/EN. When SYNC/EN
is driven with an external clock, the internal oscillator
synchronizes the rising edge of the clock at SYNC/EN to
DH going high. When being driven by a synchronization
clock signal at SYNC/EN, the controller synchronizes to
the external clock within two cycles. The frequency at
SYNC/EN needs to be within ±30% of the value set by
R
FREQ . See the Switching-Frequency Setting section.