Rainbow Electronics MAX8742 - Manual (Page 17)

MAX8741/
M
AX8742
500kHz Multi-Output Power-Supply Controllers
with High Impedance in Shutdown
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The 2.5V reference (REF) is accurate to ±2% over tem-
perature, making REF useful as a precision system ref-
erence. Bypass REF to GND with 1µF (min). REF can
supply up to 5mA for external loads. (Bypass REF with
a minimum 1µF/mA reference load current.) However, if
extremely accurate specifications for both the main out-
put voltages and REF are essential, avoid loading REF
more than 100µA. Loading REF reduces the main out-
put voltage slightly, because of the reference load-
regulation error.
When the 5V main output voltage is above 4.5V, an inter-
nal p-channel MOSFET switch connects CSL5 to V
L ,
while simultaneously shutting down the V L linear regula-
tor. This action bootstraps the IC, powering the internal
circuitry from the output voltage, rather than through a
linear regulator from the battery. Bootstrapping reduces
power dissipation due to gate charge and quiescent
losses by providing that power from a 90%-efficient
switch-mode source, rather than from a much-less-effi-
cient linear regulator.
Boost High-Side Gate-Drive Supply
(BST3 and BST5)
Gate-drive voltage for the high-side n-channel switches is
generated by a flying-capacitor boost circuit (Figure 2).
The capacitor between BST_ and LX_ is alternately
charged from the V
L supply and placed parallel to the
high-side MOSFET’s gate-source terminals. On startup,
the synchronous rectifier (low-side MOSFET) forces LX_
to 0V and charges the boost capacitors to 5V. On the
second half-cycle, the SMPS turns on the high-side
MOSFET by closing an internal switch between BST_ and
DH_. This provides the necessary enhancement voltage
to turn on the high-side switch, an action that “boosts” the
5V gate-drive signal above the battery voltage.
Ringing at the high-side MOSFET gate (DH3 and DH5)
in discontinuous-conduction mode (light loads) is a nat-
ural operating condition. It is caused by residual ener-
gy in the tank circuit, formed by the inductor and stray
capacitance at the switching node, LX. The gate-drive
negative rail is referred to LX, so any ringing there is
directly coupled to the gate-drive output.
Current-Limiting and Current-Sense
Inputs (CSH and CSL)
The current-limit circuit resets the main PWM latch and
turns off the high-side MOSFET switch whenever the
voltage difference between CSH and CSL exceeds
100mV. This limiting is effective for both current flow
directions, putting the threshold limit at ±100mV. The
tolerance on the positive current limit is ±20%, so the
external low-value sense resistor (R1) must be sized for
80mV / I
PEAK , where I PEAK is the required peak induc-
tor current to support the full load current, while compo-
nents must be designed to withstand continuous-
current stresses of 120mV/R1.
For breadboarding or for very-high-current applica-
tions, it may be useful to wire the current-sense inputs
with a twisted pair, rather than PC traces. (This twisted
pair need not be special; two pieces of wire-wrap wire
twisted together is sufficient.) This reduces the possible
noise picked up at CSH_ and CSL_, which can cause
unstable switching and reduced output current. The
CSL5 input also serves as the IC’s bootstrap supply
input. Whenever V
CSL5 > 4.5V, an internal switch con-
nects CSL5 to V L .
Oscillator Frequency and
Synchronization (SYNC)
The SYNC input controls the oscillator frequency. Low
selects 333kHz; high selects 500kHz. SYNC can also
be used to synchronize with an external 5V CMOS or
TTL clock generator. SYNC has a guaranteed 400kHz
to 583kHz capture range. A high-to-low transition on
SYNC initiates a new cycle.
Operating at 500kHz optimizes the application circuit for
component size and cost; 333kHz operation provides
increased efficiency, lower dropout, and improved load-
transient response at low input-output voltage differ-
ences (see the Low-Voltage Operation section).
Shutdown Mode
Holding SHDN low puts the IC into its 4µA shutdown
mode. SHDN is logic input with a threshold of about 1V
(the V
TH of an internal n-channel MOSFET). For automatic
startup, bypass SHDN to GND with a 0.01µF capacitor
and connect it to V+ through a 220kΩ resistor.
Power-Up Sequencing and
ON/
OFF
Controls
Startup is controlled by RUN/ON3 and TIME/ON5 in
conjunction with SEQ. With SEQ connected to REF, the
two control inputs act as separate ON/OFF controls for
each supply. With SEQ connected to V
L or GND,
RUN/ON3 becomes the master ON/OFF control input
and TIME/ON5 becomes a timing pin, with the delay
between the two supplies determined by an external
capacitor. The delay is approximately 800µs/nF. The
3.3V supply powers up first if SEQ is connected to V
L ,
and the 5V supply is first if SEQ is connected to GND.
When driving TIME/ON5 as a control input with external
logic, always place a resistor (>1kΩ) in series with the
input. This prevents possible crowbar current due to
the internal discharge pulldown transistor, which turns
on in standby mode and momentarily at the first power-
up or in shutdown mode.