Xilinx LogiCore PCI v3.0 - Manual (Page 55)

PCI v3.0.151 Getting Started Guide www.xilinx.com 55
UG157 August 31, 2005
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Chapter 7
Timing Simulation
This chapter describes how to perform timing simulation using the ping64 example design
with global clocks using the supported timing simulation tools. For the PCI 32 interface,
substitute ping32 for ping64. If you are using a design with reference clocks, substitute
pcim_top with pcim_top_r and ping_tb with ping_tb_r.
Supported timing simulation tools include
•
Cadence NC-Verilog v.5.0
•
Model Technology ModelSim v5.7b
Cadence NC-Verilog
Before attempting timing simulation, ensure that the NC-Verilog environment is properly
configured for use. In addition, you must have successfully completed the implementation
phase using the Xilinx tools.
1. Navigate to the timing simulation directory and copy the back-annotated timing
models from the implementation directory:
cd /verilog/example/post_sim
cp ../xilinx/pcim_top_routed.v .
cp ../xilinx/pcim_top_routed.sdf .
2. Edit the ping_tb.f file. This file lists command line arguments for NC-Verilog, and is
shown below:
../source/ping_tb.v
../source/stimulus.v
../source/busrecord.v
../source/dumb_arbiter.v
../source/dumb_targ32.v
../source/dumb_targ64.v
../source/glbl.v
./pcim_top_routed.v
+libext+.vmd+.v
-y /verilog/src/simprims
3. Modify the library search path by changing to match the
Xilinx installation directory and save the file.
4. To run the NC-Verilog simulation:
ncverilog -f ping_tb.f