Xilinx LogiCore PCI v3.0 - Manual (Page 41)

PCI v3.0.151 Getting Started Guide www.xilinx.com 41
UG157 August 31, 2005
Model Technology ModelSim R
3. Modify the library search path by changing to match the
Xilinx installation directory and then save the file.
Most of the files listed are related to the example design and its testbench. For other
testbenches, the following subset must be used for proper simulation of the PCI interface:
../source/glbl.v
../../src/xpci/pci_lc_i.v
../../src/xpci/pcim_lc.v
+libext+.vmd+.v
-y /verilog/src/unisims
-y /verilog/src/simprims
This list does not include any configuration file, user application, top level wrapper, or
testbench. These additional files are required for a meaningful simulation.
4. Invoke ModelSim, and ensure that the current directory is set to:
/verilog/example/func_sim
5. To run the simulation:
do modelsim.do
This compiles all modules, loads them into the simulator, displays the waveform viewer,
and runs the simulation.
VHDL
1. Navigate to the functional simulation directory:
cd /vhdl/example/func_sim
2. View the ping.files file. This file lists the individual source files required, and is
shown below:
../../src/xpci/pci_lc_i.vhd
../../src/xpci/pcim_lc.vhd
../source/cfg_ping.vhd
../source/ping.vhd
../source/pcim_top.vhd
../source/busrecord.vhd
../source/dumb_arbiter.vhd
../source/dumb_targ32.vhd
../source/dumb_targ64.vhd
../source/stimulus.vhd
../source/ping_tb.vhd
Most of the files listed are related to the example design and its testbench. For other
testbenches, the following subset must be used for proper simulation of the PCI interface:
../../src/xpci/pci_lc_i.vhd
../../src/xpci/pcim_lc.vhd
This list does not include any configuration file, user application, top level wrapper, or
testbench. These additional files are required for a meaningful simulation.
3. Invoke ModelSim, and ensure that the current directory is set to the following: