Xilinx LogiCore PCI v3.0 - Manual (Page 46)

46 www.xilinx.com PCI v3.0.151 Getting Started Guide
UG157 August 31, 2005
Chapter 5: Synthesizing a Design R
8. After adding the three final files (for a total of six source files), click OK to return to the
main project window.
9. In the Source Files list, view the list of newly added source files by double-clicking the
flowtest/verilog
folder (if it is not already open). Reorder the source files in the
folder by dragging them to list them in the hierarchical order displayed in Figure 5-10 .
10. Click Change Result File to display the EDIF Result File dialog box; then move the to
following directory:
/verilog/example/synthesis
11. Name the file pcim_top.edf and click OK to set the name of the result file and return
to the main project window.
Note : In practice, the directory for the EDIF result file does not need to be changed.
However, the sample processing scripts included with the example design assume that the
output EDIF files will be located in the synthesis directory.
12. From the main project window, click Change Target to display the Options for
Implementation dialog box, as shown in Figure 5-11 .
Figure 5-10: Main Project Window with Source Files