Xilinx IP Ethernet AVB Endpoint v2.4 UG492 - Manual (Page 39)

Ethernet AVB Endpoint User Guide www.xilinx.com 39
UG492 September 21, 2010
Chapter 5
Core Architecture
As described in Chapter 4, “Generating the Core” , the core can be generated in one of two
formats, the functionality of which is described in this chapter:
• “Standard CORE Generator Format” (provided for the standard ISE® software
environment)
This option will deliver the core in the standard CORE Generator™ output format, as
used by many other cores including previous versions of this core and all other
Ethernet LogiCORE™ IP solutions.
When generated in this format, the core is designed to interface to the LogiCORE IP
Tri-Mode Ethernet MAC or the LogiCORE IP Embedded Tri-Mode Ethernet MAC
wrappers (available in selected Virtex® families). See
Figure 5-1 .
• “EDK pcore Format” (provided for the Embedded Development Kit)
This option will deliver the core in the standard pcore format, suitable for directly
importing into the Xilinx Embedded Development Kit (EDK) environment.
When generated in this format, the core is designed to interface to the XPS LocalLink
Tri-Mode Ethernet MAC (xps_ll_temac). See
Figure 5-2 .