Directory and file contents, Project directory, Table 15-1 – Xilinx IP Ethernet AVB Endpoint v2.4 UG492 User Manual
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Ethernet AVB Endpoint User Guide
UG492 September 21, 2010
Chapter 15: Detailed Example Design (Standard Format)
Files for compiling the low-level drivers provided with the core
Data files for automatic integration into Xilinx Platform Studio
An application example using the low-level driver files
Low-level driver source C files
Directory and File Contents
The core directories and their associated files are defined in the following tables.
The project directory contains all the CORE Generator software project files.
Table 15-1:
Project Directory
Name
Description
Top-level netlist. This is instantiated by
the Verilog or VHDL example design.
Verilog or VHDL simulation model;
UniSim-based.
Verilog or VHDL instantiation template
for the core.
Log file that records the settings used to
generate a core. An XCO file is
generated by the CORE Generator
software for each core that it creates in
the current project directory. An XCO
file can also be used as an input to the
CORE Generator software.
List of files delivered with the core.