Product preview – Texas Instruments THUNDER TNETX3270 User Manual

Page 5

TNETX3270

ThunderSWITCH 24/3 ETHERNET SWITCH

WITH 24 10-MBIT/S PORTS

AND 3 10-/100-MBIT/S PORTS

SPWS043B – NOVEMBER 1997 – REVISED

APRIL

1999



POST

OFFICE BOX 655303 DALLAS,

TEXAS

75265

•

DA12–DA0

MRESET

ECLK

EDIO

DD31–DD0

DCLK

DRAS
DCAS

LEDDATA

LEDCLK

SDATA7–SDATA0

SAD1–SAD0

SRNW

SCS

SRDY

DRAM

Port

LED

Activity

Port

CPU

Interface

Serial

MII

Interface

TH0CLK

TRST

TMS

TCLK

TDI

TDO

TAP

Address

Compare

Statistics

Storage

MIB

JTAG

Test Access

Port (TAP)

EEPROM

Port

TH0TXD3–TH0TXD0

TH0TXEN
TH0COL
TH0CRS
TH0SYNC
TH0RXD3–TH0RXD0
TH0RXDV
TH0LINK

MxxTCLK
MxxTXD3–MxxTXD0
MxxTXEN
MxxTXER
MxxCOL
MxxCRS
MxxRCLK
MxxRXD3–MxxRXD0
MxxRXDV

Three Ports
(24–26)†
10/100 Mbit/s

MxxRXER
MxxFORCE10
MxxFORCEHD
MxxLINK

MDCLK

MDIO

Network

Statistics

Logic

† xx is the port number that is being monitored.

Data Path

LED

Interface

TH0RENEG

TH1CLK

TH1TXD3–TH1TXD0
TH1TXEN
TH1COL
TH1CRS
TH1SYNC
TH1RXD3–TH1RXD0
TH1RXDV

TH1LINK

TH1RENEG

TH2CLK
TH2TXD3–TH2TXD0
TH2TXEN
TH2COL
TH2CRS
TH2SYNC
TH2RXD3–TH2RXD0
TH2RXDV
TH2LINK
TH2RENEG

CPU

Interface

SDRAM

Controller

Controller (MAC)

MUX

Controller (MAC)

MII

Eight Ports
(16–23)
10 Mbit/s

Eight Ports
(08–15)
10 Mbit/s

Eight Ports
(00–07)
10 Mbit/s

Queue

Manager

EEPROM

Interface

SDMA

SINT

STXRDY

SRXRDY

Miscellaneous

Functions

OSCIN

RESET

MII

Figure 1. TNETX3270 Interface Block Diagram

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