Renesas SuperH M3A-HS86 - Manual (Page 22)

Functional Overview
2.3 Memory
Rev.1.0 Feb 06. 2007 2-4
REJ10J0916-0100
2
2.3 Memory
2.3.1 SH7086 On-chip Memory
The SH7086 includes 512-Kbyte flash memory and 32-Kbyte SRAM.
2.3.2 SDRAM
The M3A-HS86 (3.3V version) mounts 16MB SDRAM as standard equipment. SDRAM is controlled by the bus
state controller built into SH7086. Table2.3.1 lists SDRAM specifications used in M3A-HS86. Figure2.3.1 shows the
block diagram of SDRAM connection.
Table2.3.1 SDRAM Specifications
Specifications Contents
Configuration 16 Mbytes (16-bit bus) x 1pc.
Capacity 16 Mbytes
Access Time 5.4ns
CAS Latency 2(at 40MHz bus clock)
Refresh Interval 4,096 refresh cycles every 64ms
Row Address A11- A0
Column Address A8 - A0
Number of Banks 4-bank operation controlled by BA0 and BA1
SH7086
CS3
DQMLU
DQMLL
CK
CKE
RDWR
RASL
CASL
A14
A13 BA1
BA0
DQMU
CLK
DQML
CS#
R AS #
CKE
WE#
CAS
A11 -A0
SDRAM
(8M Word x 16bit)
BA1
BA0
DQ15-DQ0
DQMU
CLK
DQML
CS
RAS
CKE
WE
CAS
A11-A0 A12-A1
D15-D0
11
16
Figure2.3.1 Block Diagram of SDRAM Connection