National Instruments 653X User Manual
Page 58
Chapter 3
Timing Diagrams
© National Instruments Corporation
3-7
The 653X device can either drive an output clock signal onto the PCLK line
or receive an input clock signal from the PCLK line. By default, the PCLK
line is set for input during output transfers, and set for output during input
transfers.
Tip
If you are using long cables, slow down the PCLK clock signal to compensate for the
decrease in data setup time.
See also other documents in the category National Instruments Computer Accessories:
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- NI 78xxR (12 pages)
- PCI-6110E/6111E (113 pages)
- NI 6115/6120 (127 pages)
- 1128 (97 pages)
- 800 Series (104 pages)
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- NI 784xR (74 pages)
- GPIB-100A (43 pages)
- VXI-MIO Series (151 pages)
- Low-Cost Multifunction I/O Board for ISA Lab-PC+ (211 pages)
- PC-DIO-24/PnP (107 pages)
- PC-LPM-16/PnP (125 pages)
- NI 7831R (71 pages)
- VXI/VME 600 (61 pages)
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- PC-DIO-96 (105 pages)
- NI UES-3880 (14 pages)
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- AT-MIO-16X (330 pages)
- 7340 PCI (67 pages)
- NI 783xR (73 pages)
- NI CVS-1450 Series (91 pages)
- SCXI-1321 (16 pages)