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Manual configuration, Main text summary, Key information – Panasonic MN101C00 User Manual

Page 5: Supplementary information, Precautions and warnings, The smallest block in this manual, Important information from the text, 3 16-bit timer operation (timer 4)

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How to Read This Manual–2

Manual Configuration

Each section of this manual consists of a title, summary, main text, supplemental information, precautions and

warnings. The layout and definition of each section are shown below.

Subtitle

Sub-subtitle

The smallest block
in this manual.

Main text

Summary

Introduction to the
section.

Key information

Important
information from
the text.

Supplementary
information

Supplementary
information for the
main text. An
explanation of
terminology is also
included.

Precautions and
warnings

Precautions are
listed in case of lost
functionality or
damage.
Be sure to read.

Chapter 4 Timer Functions

83

4-3 16-bit Timer Operation (timer 4)

4-3-1 Overview

Timer 4 is a 16-bit programmable counter that can be used as an event counter.

A signal with frequency of 1/2 of the timer 4 overflow signal can be output from the

TM4IO pin. An input capture function and added pulse PWM output function can

also be used.

■ Timer Operation

Settings for timer operation are listed below.

(1)

Set the TM4EN flag of the timer 4 mode register (TM4MD) to "0" so that the count

operation of timer 4 is stopped.

(2)

Set the TM4CK2~0 flags of the TM4MD register to select fosc, fs/4, or fs/16 as the

clock source.

(3)

Set the TM4PWM flag of the TM4MD register to "0" so that 16-bit timer operation is

selected.

Figure 4-3-1 Binary Counter 4 (TM4BC) Count Timing

16-bit Timer Operation (timer 4)

When servicing an interrupt, reset

the timer 4 interrupt request flag

before operating timer 4.

During a count operation, be

careful if the value set in TM4OCH

and TM4OCL is smaller than the

value of binary counter 4, since

the count-up operation will

continue until overflow occurs.

Clock

TM4EN

Binary

counter 4

Write to registers

TM4OCH, TM4OCL

05

04

06

07

08

09

00

If the TM4EN flag of the TM4MD register is changed

simultaneously with other bits, the switching operation may cause

binary counter 4 to be incremented.

If the value of TM4OCH and TM4OCL registers is overwritten while

timer 4 has stopped counting, binary counter 4 will be reset to

X'0000'.