Intel D15343-003 - Manual (Page 82)

Intel
®
82854 Graphics Memory Controller Hub (GMCH)
82 D15343-003
11 Activate to Precharge delay (tRAS), MAX :
This bit controls the maximum number of clocks that a DDR SDRAM bank can remain open. After
this time period, the system memory Controller will guarantee to pre-charge the bank. Note that
this time period may or may not be set to overlap with time period that requires a refresh to
happen.
The DDR SDRAM Controller includes a separate tRAS-MAX counter for every supported bank.
With a maximum of four rows and four banks per row, there are 16 counters.
0: 120 micro-seconds
1: Reserved.
10:9 Activate to Precharge delay (tRAS), MIN :
This bit controls the number of DDR SDRAM clocks for tRAS MIN
00: 8 Clocks
01: 7 Clocks
10: 6 Clocks
11: 5 Clocks
8:7 Reserved
6:5 CAS# Latency (tCL) :
Encoding DDR SDRAM CL
00: 2.5
01: 2
10: Reserved
11: Reserved
4 Reserved
3:2 DDR SDRAM RAS# to CAS# Delay (tRCD): This bit controls the number of clocks inserted
between a Row Activate command and a Read or Write command to that row.
Encoding
tRCD
00: 4 DDR SDRAM Clocks (DDR 333 SDRAM)
01: 3 DDR SDRAM Clocks
10: 2 DDR SDRAM Clocks
11: Reserved
1:0 DDR SDRAM RAS# Precharge (tRP): This bit controls the number of clocks that are inserted
between a row precharge command and an activate command to the same row.
Encoding
tRP
00: 4 DDR SDRAM Clocks (DDR 333 SDRAM)
01: 3 DDR SDRAM Clocks
10: 2 DDR SDRAM Clocks
11: Reserved