Intel D15343-003 - Manual (Page 7)

D15343-003 7
Contents
Figures
1 Intel® 854 Chipset system block diagram (Native Graphic mode) .............................................16
2 Configuration Address Register..................................................................................................45
3 Configuration Data Register .......................................................................................................47
4 PAM Registers............................................................................................................................62
5 Simplified View of System Address Map ..................................................................................111
6 Detailed View of System Address Map.....................................................................................112
7 Intel
®
82854 GMCH Graphics Block Diagram (Native Graphic Mode only) .............................126
8 ARIB TR-B15 Plane Resolutions ..............................................................................................139
9 H, V Parameters .......................................................................................................................140
10 Interlaced Timing Using HSYNC and VSYNC for Field1/Field2 Downstream Detection..........140
11 Timing Register Switching ........................................................................................................144
12 Intel
® 82854 GMCH Ballout Diagram (Top View).....................................................................153
13 Intel
®
82854 GMCH Micro-FCBGA Package Dimensions (Top View) .....................................164
14 Intel
®
82854 GMCH Micro-FCBGA Package Dimensions (Side View) ....................................165
15 Intel ® 82854 GMCH Micro-FCBGA Package Dimensions (Bottom View) ................................166
Tables
1 Terms and Descriptions..............................................................................................................17
2 Reference Documents ................................................................................................................19
3 DDR SDRAM Memory Capacity .................................................................................................22
4 Intel ® 82854 GMCH Interface Clocks .........................................................................................25
5 Host Interface Signal Descriptions..............................................................................................28
6 DDR SDRAM Interface Descriptions .........................................................................................31
7 Hub Interface Signals ................................................................................................................32
8 Clock Signals ..............................................................................................................................33
9 Digital Video Output B (DVOB) Port Signal Descriptions ...........................................................35
10 Digital Video Output C (DVOC) Port Signal Descriptions ...........................................................36
11 DVOB and DVOC Port Common Signal Descriptions ...............................................................37
12 Analog CRT Display Signal Descriptions....................................................................................37
13 GPIO Signal Descriptions ...........................................................................................................38
14 Voltage References, PLL Power ................................................................................................39
15 Device Number Assignment .......................................................................................................41
16 Nomenclature for Access Attributes ...........................................................................................42
17 VGA I/O Mapped Register List ...................................................................................................48
18 Index – Data Registers ...............................................................................................................48
19 GMCH Configuration Space - Device #0, Function#0 ................................................................49
20 Attribute Bit Assignment .............................................................................................................61
21 PAM Registers and Associated System Memory Segments ......................................................63
22 Host-Hub I/F Bridge/System Memory Controller Configuration Space (Device #0, Function#1) 72
23 Configuration Process Configuration Space (Device#0, Function #3)........................................92
24 Intel
® 82854 GMCH Configurations and Some Resolution Examples: Native Graphics Mode.99
25 Integrated Graphics Device Configuration Space (Device #2, Function#0) ............................100
26 System Memory Segments and Their Attributes ......................................................................113
27 Table 33. Pre-allocated System Memory..................................................................................115
28 SMM Space Transaction Handling ...........................................................................................119