Intel D15343-003 - Manual (Page 26)

Intel
®
82854 Graphics Memory Controller Hub (GMCH)
26 D15343-003
2.9 System Interrupts
The GMCH supports both the legacy Intel 8259 Programmable Interrupt delivery mechanism and
the Intel Celeron M processor FSB interrupt delivery mechanism. The serial APIC Interrupt
mechanism is not supported.
The Intel 8259 Interrupt delivery mechanism support consists of flushing in bound Hub interface
write buffers when an Interrupt Acknowledge cycle is forwarded from the system bus to the Hub
interface.
PCI MSI interrupts are generated as memory writes. The GMCH decodes upstream memory writes
to the range 0FEE0_0000h - 0FEEF_FFFFh from the Hub interface as message based interrupts.
The GMCH forwards the memory writes along with the associated write data to the system bus as
an Interrupt Message transaction. Since this address does not decode as part of main system
memory, the write cycle and the write data do not get forwarded to system memory via the write
buffer. The GMCH provides the response and HTRDY# for all Interrupt Message cycles including
the ones originating from the GMCH. The GMCH also supports interrupt redirection for upstream
interrupt memory writes.
For message based interrupts, system write buffer coherency is maintained by relying on strict
ordering of memory writes. The GMCH ensures that all memory writes received from a given
interface prior to an interrupt message memory write are delivered to the system bus for snooping
in the same order that they occur on the given interface.