Intel D15343-003 - Manual (Page 38)

Intel
®
854 Graphics Memory Controller Hub (GMCH)
38 D15343-003
3.5.4 General Purpose Input/Output Signals
Table 13. GPIO Signal Descriptions
GPIO I/F Total Type Comments
RSTIN# I
CMOS
Reset: Primary Reset, Connected to PCIRST# of ICH4-M.
PWROK I
CMOS
Power OK : Indicates that power to GMCH is stable.
EXTTS_0 I
CMOS
External Thermal Sensor Input: This signal is an active low input to the
GMCH and is used to monitor the thermal condition around the system memory
and is used for triggering a read throttle. The GMCH can be optionally
programmed to send a SERR, SCI, or SMI message to the ICH4-M upon the
triggering of this signal.
LCLKCTLA O
CMOS
SSC Chip Clock Control: Can be used to control an external clock chip with
SSC control.
LCLKCTLB O
CMOS
SSC Chip Data Control: Can be used to control an external clock chip for
SSC control.
DDCACLK I/O
CMOS
CRT DDC Clock: This signal is used as the DDC clock signal between the
CRT monitor and the GMCH.
DDCADATA I/O
CMOS
CRT DDC Data: This signal is used as the DDC data signal between the CRT
monitor and the GMCH.
MI2CCLK I/O
DVO
DVO I2C Clock: This signal is used as the I2C_CLK for a digital display (i.e.
TV-Out Encoder, TMDS transmitter). This signal is tri-stated during a hard
reset.
MI2CDATA I/O
DVO
DVO I2C Data: This signal is used as the I2C_DATA for a digital display (i.e.
TV-Out Encoder, TMDS transmitter). This signal is tri-stated during a hard
reset.
MDVICLK I/O
DVO
DVI DDC Clock: This signal is used as the DDC clock for a digital display
connector (that is, primary digital monitor). This signal is tri-stated during a hard
reset.
MDVIDATA I/O
DVO
DVI DDC Data: The signal is used as the DDC data for a digital display
connector (that is, the primary digital monitor). This signal is tri-stated during a
hard reset.
MDDCDATA I/O
DVO
DVI DDC Clock: The signal is used as the DDC data for a digital display
connector (that is, the secondary digital monitor). This signal is tri-stated during
a hard reset.
MDDCCLK I/O
DVO
DVI DDC Data: The signal is used as the DDC clock for a digital display
connector (that is, the secondary digital monitor). This signal is tri-stated during
a hard reset.